[llvm-commits] [llvm] r93667 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp test/CodeGen/X86/bigstructret2.ll
Kenneth Uildriks
kennethuil at gmail.com
Sat Jan 16 15:37:33 PST 2010
Author: kennethuil
Date: Sat Jan 16 17:37:33 2010
New Revision: 93667
URL: http://llvm.org/viewvc/llvm-project?rev=93667&view=rev
Log:
When checking for sret-demotion, it needs to use legal types. When using the return value of an sret-demoted call, it needs to use possibly illegal types that match the declared Type of the callee.
Added:
llvm/trunk/test/CodeGen/X86/bigstructret2.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=93667&r1=93666&r2=93667&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sat Jan 16 17:37:33 2010
@@ -800,18 +800,19 @@
SDNodeOrder, Chain, NULL);
}
-/// Get the EVTs and ArgFlags collections that represent the return type
-/// of the given function. This does not require a DAG or a return value, and
-/// is suitable for use before any DAGs for the function are constructed.
+/// Get the EVTs and ArgFlags collections that represent the legalized return
+/// type of the given function. This does not require a DAG or a return value,
+/// and is suitable for use before any DAGs for the function are constructed.
static void getReturnInfo(const Type* ReturnType,
Attributes attr, SmallVectorImpl<EVT> &OutVTs,
SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
TargetLowering &TLI,
SmallVectorImpl<uint64_t> *Offsets = 0) {
SmallVector<EVT, 4> ValueVTs;
- ComputeValueVTs(TLI, ReturnType, ValueVTs, Offsets);
+ ComputeValueVTs(TLI, ReturnType, ValueVTs);
unsigned NumValues = ValueVTs.size();
- if ( NumValues == 0 ) return;
+ if (NumValues == 0) return;
+ unsigned Offset = 0;
for (unsigned j = 0, f = NumValues; j != f; ++j) {
EVT VT = ValueVTs[j];
@@ -834,6 +835,9 @@
unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
+ unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
+ PartVT.getTypeForEVT(ReturnType->getContext()));
+
// 'inreg' on function refers to return value
ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
if (attr & Attribute::InReg)
@@ -848,6 +852,11 @@
for (unsigned i = 0; i < NumParts; ++i) {
OutVTs.push_back(PartVT);
OutFlags.push_back(Flags);
+ if (Offsets)
+ {
+ Offsets->push_back(Offset);
+ Offset += PartSize;
+ }
}
}
}
@@ -5098,16 +5107,37 @@
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
MVT::Other, &Chains[0], NumValues);
PendingLoads.push_back(Chain);
+
+ // Collect the legal value parts into potentially illegal values
+ // that correspond to the original function's return values.
+ SmallVector<EVT, 4> RetTys;
+ RetTy = FTy->getReturnType();
+ ComputeValueVTs(TLI, RetTy, RetTys);
+ ISD::NodeType AssertOp = ISD::DELETED_NODE;
+ SmallVector<SDValue, 4> ReturnValues;
+ unsigned CurReg = 0;
+ for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
+ EVT VT = RetTys[I];
+ EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
+ unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
+
+ SDValue ReturnValue =
+ getCopyFromParts(DAG, getCurDebugLoc(), SDNodeOrder, &Values[CurReg], NumRegs,
+ RegisterVT, VT, AssertOp);
+ ReturnValues.push_back(ReturnValue);
+ if (DisableScheduling)
+ DAG.AssignOrdering(ReturnValue.getNode(), SDNodeOrder);
+ CurReg += NumRegs;
+ }
+ SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+ DAG.getVTList(&RetTys[0], RetTys.size()),
+ &ReturnValues[0], ReturnValues.size());
- SDValue MV = DAG.getNode(ISD::MERGE_VALUES,
- getCurDebugLoc(),
- DAG.getVTList(&OutVTs[0], NumValues),
- &Values[0], NumValues);
- setValue(CS.getInstruction(), MV);
+ setValue(CS.getInstruction(), Res);
if (DisableScheduling) {
DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
- DAG.AssignOrdering(MV.getNode(), SDNodeOrder);
+ DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
}
}
Added: llvm/trunk/test/CodeGen/X86/bigstructret2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bigstructret2.ll?rev=93667&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bigstructret2.ll (added)
+++ llvm/trunk/test/CodeGen/X86/bigstructret2.ll Sat Jan 16 17:37:33 2010
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -o %t
+
+%0 = type { i64, i64 }
+
+declare fastcc %0 @ReturnBigStruct() nounwind readnone
+
+define void @test(%0* %p) {
+ %1 = call fastcc %0 @ReturnBigStruct()
+ store %0 %1, %0* %p
+ ret void
+}
+
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