[llvm-commits] [llvm] r93204 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel.ll

[Benjamin Kramer]

Am 11.01.2010 um 23:59 schrieb Evan Cheng:

> Author: evancheng
> Date: Mon Jan 11 16:59:27 2010
> New Revision: 93204
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=93204&view=rev
> Log:
> Add manual ISD::OR fastisel selection routines. TableGen is no longer autogen them after 93152 and 93191.
> 
> Modified:
>    llvm/trunk/lib/Target/X86/X86FastISel.cpp
>    llvm/trunk/test/CodeGen/X86/fast-isel.ll
> 
> Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=93204&r1=93203&r2=93204&view=diff
> 
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Mon Jan 11 16:59:27 2010
> @@ -104,6 +104,8 @@
> 
>   bool X86SelectBranch(Instruction *I);
> 
> +  bool X86SelectOR(Instruction *I);
> +
>   bool X86SelectShift(Instruction *I);
> 
>   bool X86SelectSelect(Instruction *I);
> @@ -945,6 +947,44 @@
>   return true;
> }
> 
> +bool X86FastISel::X86SelectOR(Instruction *I) {
> +  // FIXME: This is necessary because tablegen stopped generate fastisel
> +  // patterns after 93152 and 93191 (which turns OR to ADD if the set
> +  // bits in the source operands are known not to overlap).
> +  const TargetRegisterClass *RC = NULL;
> +  unsigned OpReg = 0, OpImm = 0;
> +  if (I->getType()->isInteger(16)) {
> +    RC = X86::GR16RegisterClass;
> +    OpReg = X86::OR16rr; OpImm = X86::OR16ri;
> +  } else if (I->getType()->isInteger(32)) {
> +    RC = X86::GR32RegisterClass;
> +    OpReg = X86::OR32rr; OpImm = X86::OR32ri;
> +  } else if (I->getType()->isInteger(64)) {
> +    RC = X86::GR64RegisterClass;
> +    OpReg = X86::OR32rr; OpImm = X86::OR32ri;
                      ^^                   ^^

Hi Evan,

I believe this patch is breaking bootstrap on x86_64. Testcase attached.

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