[llvm-commits] [llvm] r92810 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

[Bill Wendling]

Author: void
Date: Tue Jan  5 18:23:35 2010
New Revision: 92810

URL: http://llvm.org/viewvc/llvm-project?rev=92810&view=rev
Log:
The previous code could potentially cause a cycle. Allow ordering w.r.t. a 0 order.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=92810&r1=92809&r2=92810&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Jan  5 18:23:35 2010
@@ -1129,8 +1129,8 @@
 
   // Prefer an ordering where the lower the non-zero order number, the higher
   // the preference.
-  if (LOrder && ROrder && LOrder != ROrder)
-    return LOrder < ROrder;
+  if ((LOrder || ROrder) && LOrder != ROrder)
+    return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
 
   unsigned LPriority = SPQ->getNodePriority(left);
   unsigned RPriority = SPQ->getNodePriority(right);