[llvm-commits] [llvm] r91993 - in /llvm/trunk: lib/Target/PIC16/PIC16ISelDAGToDAG.h lib/Target/PIC16/PIC16ISelLowering.cpp lib/Target/PIC16/PIC16ISelLowering.h test/CodeGen/PIC16/C16-49.ll
Sanjiv Gupta
sanjiv.gupta at microchip.com
Wed Dec 23 01:46:02 PST 2009
Author: sgupta
Date: Wed Dec 23 03:46:01 2009
New Revision: 91993
URL: http://llvm.org/viewvc/llvm-project?rev=91993&view=rev
Log:
Reverting back 91904.
Modified:
llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.h
llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
llvm/trunk/test/CodeGen/PIC16/C16-49.ll
Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.h?rev=91993&r1=91992&r2=91993&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.h Wed Dec 23 03:46:01 2009
@@ -36,10 +36,7 @@
public:
explicit PIC16DAGToDAGISel(PIC16TargetMachine &tm) :
SelectionDAGISel(tm),
- TM(tm), PIC16Lowering(*TM.getTargetLowering()) {
- // Keep PIC16 specific DAGISel to use during the lowering
- PIC16Lowering.ISel = this;
- }
+ TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
// Pass Name
virtual const char *getPassName() const {
Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=91993&r1=91992&r2=91993&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Dec 23 03:46:01 2009
@@ -1482,8 +1482,7 @@
// operand no. of the operand to be converted in 'MemOp'. Remember, PIC16 has
// no instruction that can operation on two registers. Most insns take
// one register and one memory operand (addwf) / Constant (addlw).
-bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp,
- SelectionDAG &DAG) {
+bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) {
// If one of the operand is a constant, return false.
if (Op.getOperand(0).getOpcode() == ISD::Constant ||
Op.getOperand(1).getOpcode() == ISD::Constant)
@@ -1492,33 +1491,11 @@
// Return false if one of the operands is already a direct
// load and that operand has only one use.
if (isDirectLoad(Op.getOperand(0))) {
- if (Op.getOperand(0).hasOneUse()) {
- // Legal and profitable folding check uses the NodeId of DAG nodes.
- // This NodeId is assigned by topological order. Therefore first
- // assign topological order then perform legal and profitable check.
- // Note:- Though this ordering is done before begining with legalization,
- // newly added node during legalization process have NodeId=-1 (NewNode)
- // therefore before performing any check proper ordering of the node is
- // required.
- DAG.AssignTopologicalOrder();
-
- // Direct load operands are folded in binary operations. But before folding
- // verify if this folding is legal. Fold only if it is legal otherwise
- // convert this direct load to a separate memory operation.
- if(ISel->IsLegalAndProfitableToFold(Op.getOperand(0).getNode(),
- Op.getNode(), Op.getNode()))
- return false;
- else
- MemOp = 0;
- }
+ if (Op.getOperand(0).hasOneUse())
+ return false;
+ else
+ MemOp = 0;
}
-
- // For operations that are non-cummutative there is no need to check
- // for right operand because folding right operand may result in
- // incorrect operation.
- if (! SelectionDAG::isCommutativeBinOp(Op.getOpcode()))
- return true;
-
if (isDirectLoad(Op.getOperand(1))) {
if (Op.getOperand(1).hasOneUse())
return false;
@@ -1537,7 +1514,7 @@
assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
unsigned MemOp = 1;
- if (NeedToConvertToMemOp(Op, MemOp, DAG)) {
+ if (NeedToConvertToMemOp(Op, MemOp)) {
// Put one value on stack.
SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
@@ -1556,7 +1533,7 @@
assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
DebugLoc dl = Op.getDebugLoc();
unsigned MemOp = 1;
- if (NeedToConvertToMemOp(Op, MemOp, DAG)) {
+ if (NeedToConvertToMemOp(Op, MemOp)) {
// Put one value on stack.
SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
@@ -1587,8 +1564,7 @@
// Nothing to do if the first operand is already a direct load and it has
// only one use.
- unsigned MemOp = 0;
- if (! NeedToConvertToMemOp(Op, MemOp, DAG))
+ if (isDirectLoad(Op.getOperand(0)) && Op.getOperand(0).hasOneUse())
return Op;
// Put first operand on stack.
Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h?rev=91993&r1=91992&r2=91993&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h Wed Dec 23 03:46:01 2009
@@ -18,7 +18,6 @@
#include "PIC16.h"
#include "PIC16Subtarget.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetLowering.h"
#include <map>
@@ -217,9 +216,7 @@
// This function checks if we need to put an operand of an operation on
// stack and generate a load or not.
- // DAG parameter is required to access DAG information during
- // analysis.
- bool NeedToConvertToMemOp(SDValue Op, unsigned &MemOp, SelectionDAG &DAG);
+ bool NeedToConvertToMemOp(SDValue Op, unsigned &MemOp);
/// Subtarget - Keep a pointer to the PIC16Subtarget around so that we can
/// make the right decision when generating code for different targets.
@@ -242,11 +239,6 @@
// Check if operation has a direct load operand.
inline bool isDirectLoad(const SDValue Op);
- public:
- // Keep a pointer to SelectionDAGISel to access its public
- // interface (It is required during legalization)
- SelectionDAGISel *ISel;
-
private:
// The frameindexes generated for spill/reload are stack based.
// This maps maintain zero based indexes for these FIs.
Modified: llvm/trunk/test/CodeGen/PIC16/C16-49.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PIC16/C16-49.ll?rev=91993&r1=91992&r2=91993&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PIC16/C16-49.ll (original)
+++ llvm/trunk/test/CodeGen/PIC16/C16-49.ll Wed Dec 23 03:46:01 2009
@@ -1,15 +0,0 @@
-;RUN: llvm-as < %s | llc -march=pic16
-
- at aa = global i16 55, align 1 ; <i16*> [#uses=1]
- at bb = global i16 44, align 1 ; <i16*> [#uses=1]
- at PORTD = external global i8 ; <i8*> [#uses=1]
-
-define void @foo() nounwind {
-entry:
- %tmp = volatile load i16* @aa ; <i16> [#uses=1]
- %tmp1 = volatile load i16* @bb ; <i16> [#uses=1]
- %sub = sub i16 %tmp, %tmp1 ; <i16> [#uses=1]
- %conv = trunc i16 %sub to i8 ; <i8> [#uses=1]
- store i8 %conv, i8* @PORTD
- ret void
-}
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