[llvm-commits] [llvm] r91944 - in /llvm/trunk/lib/Target/ARM: ARMInstrThumb.td ARMRegisterInfo.td

[Chris Lattner]

On Dec 22, 2009, at 3:54 PM, Jakob Stoklund Olesen wrote:

> Author: stoklund
> Date: Tue Dec 22 17:54:44 2009
> New Revision: 91944
>
> URL: http://llvm.org/viewvc/llvm-project?rev=91944&view=rev
> Log:
> Add a SPR register class to the ARM target.
>
> Certain Thumb instructions require only SP (e.g. tSTRspi).

Hi Jakob,

If it only allows one register, doesn't it make more sense to make it  
an implicit reg operand instead of a regclass operand?

-Chris

>
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=91944&r1=91943&r2=91944&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Dec 22 17:54:44  
> 2009
> @@ -113,7 +113,7 @@
> def t_addrmode_sp : Operand<i32>,
>                     ComplexPattern<i32, 2, "SelectThumbAddrModeSP",  
> []> {
>   let PrintMethod = "printThumbAddrModeSPOperand";
> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
> +  let MIOperandInfo = (ops JustSP:$base, i32imm:$offsimm);
> }
>
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=91944&r1=91943&r2=91944&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Tue Dec 22 17:54:44  
> 2009
> @@ -367,6 +367,19 @@
> // Condition code registers.
> def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
>
> +// Just the stack pointer (for tSTRspi and friends).
> +def JustSP : RegisterClass<"ARM", [i32], 32, [SP]> {
> +  let MethodProtos = [{
> +    iterator allocation_order_end(const MachineFunction &MF) const;
> +  }];
> +  let MethodBodies = [{
> +      JustSPClass::iterator
> +      JustSPClass::allocation_order_end(const MachineFunction &MF)  
> const {
> +        return allocation_order_begin(MF);
> +      }
> +  }];
> +}
> +
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
> // Subregister Set Definitions... now that we have all of the  
> pieces, define the
> // sub registers for each register.
>
>
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