[llvm-commits] [llvm] r91922 - /llvm/trunk/lib/CodeGen/MachineVerifier.cpp

[Jakob Stoklund Olesen]

Author: stoklund
Date: Tue Dec 22 15:48:20 2009
New Revision: 91922

URL: http://llvm.org/viewvc/llvm-project?rev=91922&view=rev
Log:
Allow explicit %reg0 operands beyond what the .td file describes.

ARM uses these to indicate predicates.

Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=91922&r1=91921&r2=91922&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Dec 22 15:48:20 2009
@@ -553,7 +553,8 @@
         report("Explicit operand marked as implicit", MO, MONum);
     }
   } else {
-    if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic())
+    // ARM adds %reg0 operands to indicate predicates. We'll allow that.
+    if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
       report("Extra explicit operand on non-variadic instruction", MO, MONum);
   }