[llvm-commits] [llvm] r91919 - in /llvm/trunk: lib/Target/X86/Disassembler/X86Disassembler.cpp lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h utils/TableGen/X86RecognizableInstr.cpp

[Sean Callanan]

Author: spyffe
Date: Tue Dec 22 15:12:55 2009
New Revision: 91919

URL: http://llvm.org/viewvc/llvm-project?rev=91919&view=rev
Log:
Fixes to the X86 disassembler:
Made LEA memory operands emit only 4 MCInst operands.
Made the scale operand equal 1 for instructions that have no
SIB byte.

Modified:
    llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
    llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
    llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp

Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=91919&r1=91918&r2=91919&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Tue Dec 22 15:12:55 2009
@@ -183,8 +183,12 @@
 /// @param mcInst       - The MCInst to append to.
 /// @param insn         - The instruction to extract Mod, R/M, and SIB fields
 ///                       from.
+/// @param sr           - Whether or not to emit the segment register.  The
+///                       LEA instruction does not expect a segment-register
+///                       operand.
 static void translateRMMemory(MCInst &mcInst,
-                              InternalInstruction &insn) {
+                              InternalInstruction &insn,
+                              bool sr) {
   // Addresses in an MCInst are represented as five operands:
   //   1. basereg       (register)  The R/M base, or (if there is a SIB) the 
   //                                SIB base
@@ -209,7 +213,7 @@
       default:
         llvm_unreachable("Unexpected sibBase");
 #define ENTRY(x)                                          \
-      case SIB_BASE_##x:                                \
+      case SIB_BASE_##x:                                  \
         baseReg = MCOperand::CreateReg(X86::x); break;
       ALL_SIB_BASES
 #undef ENTRY
@@ -222,7 +226,7 @@
       switch (insn.sibIndex) {
       default:
         llvm_unreachable("Unexpected sibIndex");
-#define ENTRY(x)                                            \
+#define ENTRY(x)                                          \
       case SIB_INDEX_##x:                                 \
         indexReg = MCOperand::CreateReg(X86::x); break;
       EA_BASES_32BIT
@@ -286,6 +290,8 @@
             break;
       }
     }
+    
+    scaleAmount = MCOperand::CreateImm(1);
   }
   
   displacement = MCOperand::CreateImm(insn.displacement);
@@ -306,7 +312,9 @@
   mcInst.addOperand(scaleAmount);
   mcInst.addOperand(indexReg);
   mcInst.addOperand(displacement);
-  mcInst.addOperand(segmentReg);
+  
+  if (sr)
+    mcInst.addOperand(segmentReg);
 }
 
 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
@@ -356,7 +364,10 @@
   case TYPE_M1616:
   case TYPE_M1632:
   case TYPE_M1664:
-    translateRMMemory(mcInst, insn);
+    translateRMMemory(mcInst, insn, true);
+    break;
+  case TYPE_LEA:
+    translateRMMemory(mcInst, insn, false);
     break;
   }
 }

Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h?rev=91919&r1=91918&r2=91919&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h Tue Dec 22 15:12:55 2009
@@ -245,6 +245,7 @@
   ENUM_ENTRY(TYPE_M16,        "2-byte")                                        \
   ENUM_ENTRY(TYPE_M32,        "4-byte")                                        \
   ENUM_ENTRY(TYPE_M64,        "8-byte")                                        \
+  ENUM_ENTRY(TYPE_LEA,        "Effective address")                             \
   ENUM_ENTRY(TYPE_M128,       "16-byte (SSE/SSE2)")                            \
   ENUM_ENTRY(TYPE_M1616,      "2+2-byte segment+offset address")               \
   ENUM_ENTRY(TYPE_M1632,      "2+4-byte")                                      \

Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=91919&r1=91918&r2=91919&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Tue Dec 22 15:12:55 2009
@@ -817,9 +817,9 @@
   TYPE("brtarget",            TYPE_RELv)
   TYPE("brtarget8",           TYPE_REL8)
   TYPE("f80mem",              TYPE_M80FP)
-  TYPE("lea32mem",            TYPE_M32)
-  TYPE("lea64_32mem",         TYPE_M64)
-  TYPE("lea64mem",            TYPE_M64)
+  TYPE("lea32mem",            TYPE_LEA)
+  TYPE("lea64_32mem",         TYPE_LEA)
+  TYPE("lea64mem",            TYPE_LEA)
   TYPE("VR64",                TYPE_MM64)
   TYPE("i64imm",              TYPE_IMMv)
   TYPE("opaque32mem",         TYPE_M1616)