[llvm-commits] [llvm] r91672 - in /llvm/trunk: lib/Target/X86/X86.td lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h test/CodeGen/X86/break-sse-dep.ll

[Chris Lattner]

On Dec 21, 2009, at 10:45 AM, Evan Cheng wrote:

>>> 
>>> +def FeatureBreakSSEDep : SubtargetFeature<"break-sse-dep", "BreakSSEDep","true",
>>> +                       "Should break SSE partial update dep with load / xorps">;
>> 
>> Do we really need a feature for this?  Is this actually good for any SSE chip?
> 
> It's not clear. It's known to be an issue since CoreDuo. It's possible it will change for future u-arch so I'd leave it as a subtarget feature for now.

Unless there is a reason to have this, I'd prefer to not have it clutter up the td files.  I can't imagine a reasonable (non-scalarizing) implementation of SSE that wouldn't have this issue.

For example, you didn't add this flag to any of the AMD chips.

-Chris