[llvm-commits] [llvm-gcc-4.2] r91720 - in /llvm-gcc-4.2/trunk: build_gcc gcc/ChangeLog.apple gcc/config/arm/arm.c gcc/config/arm/arm1136jfs.md gcc/config/arm/cortex-a8.md gcc/config/arm/sync.md gcc/config/arm/t-darwin gcc/fold-const.c gcc/local-alloc.c gcc/testsuite/ChangeLog.apple gcc/testsuite/gcc.dg/6951876.c gcc/testsuite/gcc.dg/7105615.c gcc/version.c
Bob Wilson
bob.wilson at apple.com
Fri Dec 18 14:47:33 PST 2009
Author: bwilson
Date: Fri Dec 18 16:47:32 2009
New Revision: 91720
URL: http://llvm.org/viewvc/llvm-project?rev=91720&view=rev
Log:
Merge from Apple's gcc 5658 (Apple svn 155872)
Added:
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.dg/6951876.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.dg/7105615.c
Modified:
llvm-gcc-4.2/trunk/build_gcc
llvm-gcc-4.2/trunk/gcc/ChangeLog.apple
llvm-gcc-4.2/trunk/gcc/config/arm/arm.c
llvm-gcc-4.2/trunk/gcc/config/arm/arm1136jfs.md
llvm-gcc-4.2/trunk/gcc/config/arm/cortex-a8.md
llvm-gcc-4.2/trunk/gcc/config/arm/sync.md
llvm-gcc-4.2/trunk/gcc/config/arm/t-darwin
llvm-gcc-4.2/trunk/gcc/fold-const.c
llvm-gcc-4.2/trunk/gcc/local-alloc.c
llvm-gcc-4.2/trunk/gcc/testsuite/ChangeLog.apple
llvm-gcc-4.2/trunk/gcc/version.c
Modified: llvm-gcc-4.2/trunk/build_gcc
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/build_gcc?rev=91720&r1=91719&r2=91720&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/build_gcc (original)
+++ llvm-gcc-4.2/trunk/build_gcc Fri Dec 18 16:47:32 2009
@@ -123,14 +123,19 @@
ARM_LIBSTDCXX_VERSION=4.2.1
ARM_CONFIGFLAGS="--with-gxx-include-dir=/usr/include/c++/$ARM_LIBSTDCXX_VERSION"
-# If the build target is iPhone, use the iPhone SDK as the build sysroot
-# and use the tools from the iPhone platform directory. These paths have to
-# be hardcoded, at least for now, because the build system does not
-# consistently identify separate host and target SDKROOTS. (The buildit
-# script currently sets SDKROOT to the target iPhone SDK, but XBS sets it
-# to the default host SDK "/".)
-if [ "x$RC_TARGET_CONFIG" = "xiPhone" ]; then
+if [ -n "$ARM_SDK" ]; then
+ ARM_PLATFORM=`xcodebuild -version -sdk $ARM_SDK PlatformPath`
+ ARM_SYSROOT=`xcodebuild -version -sdk $ARM_SDK Path`
+ ARM_TOOLROOT=$ARM_PLATFORM/Developer
+
+elif [ "x$RC_TARGET_CONFIG" = "xiPhone" ]; then
+
+ # If the build target is iPhone, use the iPhone SDK as the build sysroot
+ # and use the tools from the iPhone platform directory. FIXME: This is a
+ # temporary fallback for builds where ARM_SDK is not set. It can be removed,
+ # along with the following bootstrap SDK fallback, when ARM_SDK is set for
+ # all builds.
ARM_PLATFORM=/Developer/Platforms/iPhoneOS.platform
ARM_IPHONE_SDK=iPhoneOS${IPHONEOS_DEPLOYMENT_TARGET}.Internal.sdk
Modified: llvm-gcc-4.2/trunk/gcc/ChangeLog.apple
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/ChangeLog.apple?rev=91720&r1=91719&r2=91720&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/ChangeLog.apple (original)
+++ llvm-gcc-4.2/trunk/gcc/ChangeLog.apple Fri Dec 18 16:47:32 2009
@@ -1,3 +1,52 @@
+2009-12-04 Jim Grosbach <grosbach at apple.com>
+
+ Radar 6930582
+ * config/arm/arm1136jfs.md: Adjust load latencies up by one.
+ * config/arm/cortex-a8.md: Adjust load latencies up by one.
+
+2009-12-04 Jim Grosbach <grosbach at apple.com>
+
+ Radar 7393136
+ * config/arm/arm.c (arm_split_compare_and_swap): Just use a data
+ memory barrier after the strex. dsb is overkill.
+ * config/arm/sync.md (arm_memory_barrier_v7): Use "dmb ish" since
+ the compiler usage is for multithreading, not external device sync.
+
+2009-12-04 Jim Grosbach <grosbach at apple.com>
+
+ Radar 7442004
+ * config/arm/t-darwin: Always build libgcc2 functions with -marm.
+
+2009-11-03 Stuart Hastings <stuart at apple.com>
+
+ Radar 6951876
+ * local-alloc.c (reg_inheritance_1): Check for int->float
+ SUBREG cast, assume it uses the pic-base. This is the
+ 32-bit float analogue to 6050374 (see below).
+
+2009-11-02 Stuart Hastings <stuart at apple.com>
+
+ Radar 7105615
+ * fold-const.c (fold_binary): When folding an unsigned
+ comparision into a signed comparision, set TREE_OVERFLOW so
+ that the loop optimizer in tree-vrp.c understands that the
+ user did not write this.
+
+2009-10-15 Jim Grosbach <grosbach at apple.com>
+
+ Radar 7295521
+ * config/arm/arm.c (arm_split_compare_and_swap): Call insns for
+ arm_memory_barrier* and arm_memory_sync* directory rather than using
+ the expander.
+ * config/arm/sync.md (memory_barrier, memory_sync): Allocate a scratch
+ register rather than forcing IP.
+ (arm_memory_barrier_v6): Match the scratch register from the expander
+ rather than forcing IP. Rename to arm_memory_barrier_v6_explicit.
+ (arm_memory_barrier_v6_explicit): New.
+ (arm_memory_sync_v6): Match the scratch register from the expander
+ rather than forcing IP. Rename to arm_memory_sync_v6_explicit.
+ (arm_memory_sync_v6_explicit): New.
+
2009-09-11 Caroline Tice <ctice at apple.com>
Radar 6419781
@@ -9,8 +58,8 @@
2009-09-08 Jim Grosbach <grosbach at apple.com>
- Radar 7174451
- * config/arm/arm.c (arm_select_dominance_cc_mode): Unordered floats.
+ Radar 7174451
+ * config/arm/arm.c (arm_select_dominance_cc_mode): Unordered floats.
2009-09-08 Jim Grosbach <grosbach at apple.com>
@@ -1468,8 +1517,8 @@
2008-07-21 Stuart Hastings <stuart at apple.com>
Radar 6050374
- * local-alloc.c (reg_inheritance_1): Check for int->fp SUBREG
- cast, assume it uses the pic-base.
+ * local-alloc.c (reg_inheritance_1): Check for int->double
+ SUBREG cast, assume it uses the pic-base.
2008-07-18 Fariborz Jahanian <fjahanian at apple.com>
Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.c?rev=91720&r1=91719&r2=91720&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/arm.c (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.c Fri Dec 18 16:47:32 2009
@@ -2421,8 +2421,22 @@
enum machine_mode mode = GET_MODE (mem);
rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CC_REGNUM);
rtx dest_cmp, oldval_cmp;
+ rtx block_scratch, block_unspec;
- emit_insn (gen_memory_barrier ());
+ block_scratch = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ block_unspec = gen_rtx_UNSPEC (BLKmode,
+ gen_rtvec (1, gen_rtx_MEM (BLKmode,
+ block_scratch)),
+ UNSPEC_BARRIER);
+
+ /* Use the insn patterns directly rather than the expander since we're
+ * post-reload here. The v6 pattern needs a scratch register and we
+ * have one here already, so just re-use it. */
+ if (arm_arch7a)
+ emit_insn (gen_arm_memory_barrier_v7 (block_scratch, block_unspec));
+ else
+ emit_insn (gen_arm_memory_barrier_v6_explicit(block_scratch,
+ block_unspec, scratch));
label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
@@ -2481,7 +2495,11 @@
x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label1, pc_rtx);
x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
- emit_insn (gen_memory_sync ());
+ if (arm_arch7a)
+ emit_insn (gen_arm_memory_barrier_v7 (block_scratch, block_unspec));
+ else
+ emit_insn (gen_arm_memory_barrier_v6_explicit(block_scratch,
+ block_unspec, scratch));
emit_label (XEXP (label2, 0));
}
/* APPLE LOCAL end 6258536 atomic builtins */
@@ -14741,7 +14759,7 @@
}
return;
- /* APPLE LOCAL 6150859 begin use NEON instructions for SF math */
+ /* APPLE LOCAL begin 6150859 use NEON instructions for SF math */
/* This code prints the double precision register name starting at
register number of the indicated single precision register. */
case 'p':
@@ -14766,7 +14784,7 @@
fprintf (stream, "d%d", (regno - FIRST_VFP_REGNUM) >> 1);
}
return;
- /* APPLE LOCAL 6150859 end use NEON instructions for SF math */
+ /* APPLE LOCAL end 6150859 use NEON instructions for SF math */
/* These two codes print the low/high doubleword register of a Neon quad
register, respectively. For pair-structure types, can also print
Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm1136jfs.md
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm1136jfs.md?rev=91720&r1=91719&r2=91720&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/arm1136jfs.md (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/arm1136jfs.md Fri Dec 18 16:47:32 2009
@@ -267,9 +267,11 @@
"11_branches")
(define_bypass 2 "11_alu_shift_reg_op"
"11_branches")
-(define_bypass 2 "11_load1,11_load2"
+;; APPLE LOCAL 6930582 load latencies
+(define_bypass 3 "11_load1,11_load2"
"11_branches")
-(define_bypass 3 "11_load34"
+;; APPLE LOCAL 6930582 load latencies
+(define_bypass 4 "11_load34"
"11_branches")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -282,7 +284,8 @@
;; if the PC is one of the registers involved, there are additional stalls
;; not modelled here. Addressing modes are also not modelled.
-(define_insn_reservation "11_load1" 3
+;; APPLE LOCAL 6930582 load latencies
+(define_insn_reservation "11_load1" 4
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "load1"))
"l_a+e_1,l_dc1,l_dc2,l_wb")
@@ -303,7 +306,8 @@
;; Load/store double words into adjacent registers. The timing and
;; latencies are different depending on whether the address is 64-bit
;; aligned. This model assumes that it is.
-(define_insn_reservation "11_load2" 3
+;; APPLE LOCAL 6930582 load latencies
+(define_insn_reservation "11_load2" 4
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "load2"))
"l_a+e_1,l_dc1,l_dc2,l_wb")
@@ -316,7 +320,8 @@
;; Load/store multiple registers. Two registers are stored per cycle.
;; Actual timing depends on how many registers are affected, so we
;; optimistically schedule a low latency.
-(define_insn_reservation "11_load34" 4
+;; APPLE LOCAL 6930582 load latencies
+(define_insn_reservation "11_load34" 5
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "load3,load4"))
"l_a+e_1,l_dc1*2,l_dc2,l_wb")
@@ -337,14 +342,16 @@
;; An alu op can start sooner after a load, if that alu op does not
;; have an early register dependency on the load
-(define_bypass 2 "11_load1"
+;; APPLE LOCAL begin 6930582 load latencies
+(define_bypass 3 "11_load1"
"11_alu_op")
-(define_bypass 2 "11_load1"
+(define_bypass 3 "11_load1"
"11_alu_shift_op"
"arm_no_early_alu_shift_value_dep")
-(define_bypass 2 "11_load1"
+(define_bypass 3 "11_load1"
"11_alu_shift_reg_op"
"arm_no_early_alu_shift_dep")
+;; APPLE LOCAL end 6930582 load latencies
(define_bypass 3 "11_loadb"
"11_alu_op")
@@ -357,10 +364,12 @@
;; A mul op can start sooner after a load, if that mul op does not
;; have an early multiply dependency
-(define_bypass 2 "11_load1"
+;; APPLE LOCAL 6930582 load latencies
+(define_bypass 3 "11_load1"
"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
"arm_no_early_mul_dep")
-(define_bypass 3 "11_load34"
+;; APPLE LOCAL 6930582 load latencies
+(define_bypass 4 "11_load34"
"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
"arm_no_early_mul_dep")
(define_bypass 3 "11_loadb"
@@ -369,7 +378,8 @@
;; A store can start sooner after a load, if that load does not
;; produce part of the address to access
-(define_bypass 2 "11_load1"
+;; APPLE LOCAL 6930582 load latencies
+(define_bypass 3 "11_load1"
"11_store1"
"arm_no_early_store_addr_dep")
(define_bypass 3 "11_loadb"
Modified: llvm-gcc-4.2/trunk/gcc/config/arm/cortex-a8.md
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/cortex-a8.md?rev=91720&r1=91719&r2=91720&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/cortex-a8.md (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/cortex-a8.md Fri Dec 18 16:47:32 2009
@@ -187,22 +187,24 @@
;; Load instructions.
;; The presence of any register writeback is ignored here.
-;; A load result has latency 3 unless the dependent instruction has
-;; no early dep, in which case it is only latency two.
+;; APPLE LOCAL begin 6930582 load latencies
+;; A load result has latency 4 unless the dependent instruction has
+;; no early dep, in which case it is only latency three.
;; We assume 64-bit alignment for doubleword loads.
-(define_insn_reservation "cortex_a8_load1_2" 3
+(define_insn_reservation "cortex_a8_load1_2" 4
(and (eq_attr "tune" "cortexa8")
(eq_attr "type" "load1,load2,load_byte"))
"cortex_a8_load_store_1")
-(define_bypass 2 "cortex_a8_load1_2"
+(define_bypass 3 "cortex_a8_load1_2"
"cortex_a8_alu")
-(define_bypass 2 "cortex_a8_load1_2"
+(define_bypass 3 "cortex_a8_load1_2"
"cortex_a8_alu_shift"
"arm_no_early_alu_shift_dep")
-(define_bypass 2 "cortex_a8_load1_2"
+(define_bypass 3 "cortex_a8_load1_2"
"cortex_a8_alu_shift_reg"
"arm_no_early_alu_shift_value_dep")
+;; APPLE LOCAL end 6930582 load latencies
;; We do not currently model the fact that loads with scaled register
;; offsets that are not LSL #2 have an extra cycle latency (they issue
Modified: llvm-gcc-4.2/trunk/gcc/config/arm/sync.md
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/sync.md?rev=91720&r1=91719&r2=91720&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/sync.md (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/sync.md Fri Dec 18 16:47:32 2009
@@ -45,8 +45,7 @@
gen_rtvec (1, gen_rtx_MEM (BLKmode,
operands[0])),
UNSPEC_BARRIER));
- XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG(SImode,
- IP_REGNUM));
+ XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH(SImode));
emit_insn (par);
DONE;
}
@@ -56,16 +55,32 @@
[(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_BARRIER))]
"TARGET_32BIT && arm_arch7a"
- "dmb"
+ "dmb\tish"
[(set_attr "length" "4")]
)
-(define_insn "arm_memory_barrier_v6"
+;; This version matches the define_expand above.
+(define_insn "arm_memory_barrier_v6_scratch"
[(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_BARRIER))
- (clobber (reg:SI IP_REGNUM))]
+ (clobber (match_scratch:SI 2 "=&r"))]
"TARGET_32BIT && arm_arch6 && !arm_arch7a"
- "mov\tip, #0\n\tmcr\tp15, 0, ip, c7, c10, 5"
+ "mov\t%2, #0\n\tmcr\tp15, 0, %2, c7, c10, 5"
+ [(set (attr "length")
+ (if_then_else (eq_attr "is_thumb" "yes")
+ (const_int 6)
+ (const_int 8)))]
+)
+
+;; This version is used directly by the compare_and_swap splitter below.
+;; That runs after reload is complete, so we cannot use a new define_scratch.
+;; reload is not available to allocate one for us.
+(define_insn "arm_memory_barrier_v6_explicit"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_BARRIER))
+ (clobber (match_operand:SI 2 "register_operand" "=&r"))]
+ "TARGET_32BIT && arm_arch6 && !arm_arch7a"
+ "mov\t%2, #0\n\tmcr\tp15, 0, %2, c7, c10, 5"
[(set (attr "length")
(if_then_else (eq_attr "is_thumb" "yes")
(const_int 6)
@@ -91,8 +106,7 @@
gen_rtx_UNSPEC_VOLATILE (BLKmode,
gen_rtvec (1, operands[0]),
UNSPEC_SYNC));
- XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG(SImode,
- IP_REGNUM));
+ XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH(SImode));
emit_insn (par);
DONE;
}
@@ -106,12 +120,28 @@
[(set_attr "length" "4")]
)
-(define_insn "arm_memory_sync_v6"
+;; This version matches the define_expand above.
+(define_insn "arm_memory_sync_v6_scratch"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec_volatile:BLK [(mem:BLK (match_operand 1))] UNSPEC_SYNC))
+ (clobber (match_scratch:SI 2 "=&r"))]
+ "TARGET_32BIT && arm_arch6 && !arm_arch7a"
+ "mov\t%2, #0\n\tmcr\tp15, 0, %2, c7, c10, 4"
+ [(set (attr "length")
+ (if_then_else (eq_attr "is_thumb" "yes")
+ (const_int 6)
+ (const_int 8)))]
+)
+
+;; This version is used directly by the compare_and_swap splitter below.
+;; That runs after reload is complete, so we cannot use a new define_scratch.
+;; reload is not available to allocate one for us.
+(define_insn "arm_memory_sync_v6_explicit"
[(set (match_operand:BLK 0 "" "")
(unspec_volatile:BLK [(mem:BLK (match_operand 1))] UNSPEC_SYNC))
- (clobber (reg:SI IP_REGNUM))]
+ (clobber (match_operand:SI 2 "register_operand" "=&r"))]
"TARGET_32BIT && arm_arch6 && !arm_arch7a"
- "mov\tip, #0\n\tmcr\tp15, 0, ip, c7, c10, 4"
+ "mov\t%2, #0\n\tmcr\tp15, 0, %2, c7, c10, 4"
[(set (attr "length")
(if_then_else (eq_attr "is_thumb" "yes")
(const_int 6)
Modified: llvm-gcc-4.2/trunk/gcc/config/arm/t-darwin
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/t-darwin?rev=91720&r1=91719&r2=91720&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/t-darwin (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/t-darwin Fri Dec 18 16:47:32 2009
@@ -70,5 +70,6 @@
endif
# APPLE LOCAL end 6611402 configurable multilib architectures
-TARGET_LIBGCC2_CFLAGS = -fno-inline
+# APPLE LOCAL 7442004 Always build multilib libgcc functions ARM mode.
+TARGET_LIBGCC2_CFLAGS = -fno-inline -marm
Modified: llvm-gcc-4.2/trunk/gcc/fold-const.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/fold-const.c?rev=91720&r1=91719&r2=91720&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/fold-const.c (original)
+++ llvm-gcc-4.2/trunk/gcc/fold-const.c Fri Dec 18 16:47:32 2009
@@ -11280,10 +11280,24 @@
if (code == LE_EXPR || code == GT_EXPR)
{
tree st;
+ /* APPLE LOCAL begin 7105615 */
+ tree ov_zero;
st = lang_hooks.types.signed_type (TREE_TYPE (arg1));
+ /*
+ * We need a zero that is NOT part of the constant
+ * pool, because we're going to set its
+ * TREE_OVERFLOW bit. If the returned
+ * CONSTANT_INT is part of the constant pool, it
+ * may be returned to another caller in another
+ * context (i.e. tree-vrp.c), who may arbitrarily
+ * *clear* this TREE_OVERFLOW bit.
+ */
+ ov_zero = copy_node (build_int_cst (st, 0));
+ TREE_OVERFLOW (ov_zero) = 1;
return fold_build2 (code == LE_EXPR ? GE_EXPR : LT_EXPR,
type, fold_convert (st, arg0),
- build_int_cst (st, 0));
+ ov_zero);
+ /* APPLE LOCAL end 7105615 */
}
}
}
Modified: llvm-gcc-4.2/trunk/gcc/local-alloc.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/local-alloc.c?rev=91720&r1=91719&r2=91720&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/local-alloc.c (original)
+++ llvm-gcc-4.2/trunk/gcc/local-alloc.c Fri Dec 18 16:47:32 2009
@@ -2679,19 +2679,24 @@
dstregno = (int)data;
#ifdef TARGET_386
- /* Ugly special case: When moving a DImode constant into an FP
- register, GCC will use the movdf_nointeger pattern, pushing the
- DImode constant into memory and loading into the '387. It looks
- like this: (set (reg:DF) (subreg:DF (reg:DI))). We're choosing
- to match the subreg; hope this is sufficient.
+ /*
+ Ugly special case: When moving a DI/SI/mode constant into an FP
+ register, GCC will use the mov/df/sf/_nointeger pattern, pushing
+ the DI/SI/mode constant into memory and loading therefrom into an
+ FP register ('387 or SSE). It looks like this: (set (reg:DF)
+ (subreg:DF (reg:DI))). We're choosing to match the subreg; hope
+ this is sufficient. See Radars 6050374 and 6951876.
*/
- if (GET_CODE (x) == SUBREG
- && GET_MODE (x) == DFmode
- && GET_MODE (SUBREG_REG (x)) == DImode)
- {
- SET_BIT (reg_inheritance_matrix[dstregno], PIC_OFFSET_TABLE_REGNUM);
- return 0;
- }
+ if (GET_CODE (x) == SUBREG)
+ if ((GET_MODE (x) == DFmode
+ && GET_MODE (SUBREG_REG (x)) == DImode)
+ ||
+ (GET_MODE (x) == SFmode
+ && GET_MODE (SUBREG_REG (x)) == SImode))
+ {
+ SET_BIT (reg_inheritance_matrix[dstregno], PIC_OFFSET_TABLE_REGNUM);
+ return 0;
+ }
#endif
if (GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/ChangeLog.apple
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/ChangeLog.apple?rev=91720&r1=91719&r2=91720&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/ChangeLog.apple (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/ChangeLog.apple Fri Dec 18 16:47:32 2009
@@ -1,3 +1,13 @@
+2009-11-03 Stuart Hastings <stuart at apple.com>
+
+ Radar 6951876
+ * gcc.dg/6951876.c: New.
+
+2009-11-02 Stuart Hastings <stuart at apple.com>
+
+ Radar 7105615
+ * gcc.dg/7105615.c: New.
+
2009-06-15 Fariborz Jahanian <fjahanian at apple.com>
Radar 6936421
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.dg/6951876.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.dg/6951876.c?rev=91720&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.dg/6951876.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.dg/6951876.c Fri Dec 18 16:47:32 2009
@@ -0,0 +1,28 @@
+/* APPLE LOCAL file 6951876 */
+/* { dg-do compile { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
+/* { dg-options "-O2" } */
+/* Kludge: assuming PIC-base labels have a particular format: */
+/* { dg-final { scan-assembler "\"L00\[0-9\]*\\\$pb\":" } } */
+extern unsigned char*GetLine(int *s, int y);
+typedef struct {
+ int dst;
+} PIXWEIGHT ;
+typedef union {
+ int i;
+ float f;
+} INTTORFLOAT;
+void __Rescale(int *src)
+{
+ int i, y;
+ INTTORFLOAT bias;
+ INTTORFLOAT f;
+ bias.i = 22;
+ for (;;)
+ {
+ GetLine(src, y);
+ float * dstata;
+ PIXWEIGHT * _p;
+ f.f-=bias.f;
+ dstata[_p->dst] += f.f;
+ }
+}
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.dg/7105615.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.dg/7105615.c?rev=91720&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.dg/7105615.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.dg/7105615.c Fri Dec 18 16:47:32 2009
@@ -0,0 +1,13 @@
+/* APPLE LOCAL file 7105615 */
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-strict-overflow" } */
+int
+main() {
+ unsigned char uch;
+ unsigned int ui = 0;
+
+ /* Original failure was an infinite loop: */
+ for (uch = 0; uch < 0x80; uch++)
+ ui = uch + ui;
+ return ui != 8128; /* Return 0 for success. */
+}
Modified: llvm-gcc-4.2/trunk/gcc/version.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/version.c?rev=91720&r1=91719&r2=91720&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/version.c (original)
+++ llvm-gcc-4.2/trunk/gcc/version.c Fri Dec 18 16:47:32 2009
@@ -11,12 +11,12 @@
/* APPLE LOCAL begin Apple version */
#ifdef ENABLE_LLVM
#ifdef LLVM_VERSION_INFO
-#define VERSUFFIX " (Based on Apple Inc. build 5653) (LLVM build " LLVM_VERSION_INFO ")"
+#define VERSUFFIX " (Based on Apple Inc. build 5658) (LLVM build " LLVM_VERSION_INFO ")"
#else
-#define VERSUFFIX " (Based on Apple Inc. build 5653) (LLVM build)"
+#define VERSUFFIX " (Based on Apple Inc. build 5658) (LLVM build)"
#endif
#else
-#define VERSUFFIX " (Based on Apple Inc. build 5653)"
+#define VERSUFFIX " (Based on Apple Inc. build 5658)"
#endif
/* APPLE LOCAL end Apple version */
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