[llvm-commits] [llvm] r91602 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[Ken Dyck]

Author: kjdyck
Date: Thu Dec 17 09:31:52 2009
New Revision: 91602

URL: http://llvm.org/viewvc/llvm-project?rev=91602&view=rev
Log:
In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of
incrementing the simple value type of the 16-bit type, which would give the
wrong type if an intemediate MVT (such as i24) were introduced.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=91602&r1=91601&r2=91602&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Dec 17 09:31:52 2009
@@ -4584,7 +4584,7 @@
                                                  MVT::v4i32, Vec),
                                      Op.getOperand(1)));
     // Transform it so it match pextrw which produces a 32-bit result.
-    EVT EltVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
+    EVT EltVT = MVT::i32;
     SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
                                     Op.getOperand(0), Op.getOperand(1));
     SDValue Assert  = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,