[llvm-commits] [llvm] r91380 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/CellSPU/and_ops.ll

[Nick Lewycky]

Evan Cheng wrote:
>
> On Dec 14, 2009, at 10:08 PM, Nick Lewycky wrote:
>
>> Evan Cheng wrote:
>>> Author: evancheng
>>> Date: Mon Dec 14 18:52:11 2009
>>> New Revision: 91380
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=91380&view=rev
>>> Log:
>>> Fold (zext (and x, cst)) ->   (and (zext x), cst).
>>
>> Again, this looks like something instcombine ought to be doing instead?
>
> Why? See my patch that use sbb to put carry bit into GPR. Target lowering can create opportunities for this transformation.

I was asking because instcombine doesn't pick one. That means that 
anyone who wants to optimize it further down the line has to check for 
both of these patterns. Instcombine should just canonicalize it down to 
one -- but it doesn't seem like either one is particularly better in 
this case, so I thought I'd see if you had an opinion from the backend 
point of view.

No biggie. This doesn't strike me as a very important transformation to 
do in the middle-end.

Nick

> Evan
>
>>
>> Nick
>>
>>>
>>> Modified:
>>>      llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>>      llvm/trunk/test/CodeGen/CellSPU/and_ops.ll
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=91380&r1=91379&r2=91380&view=diff
>>>
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Dec 14 18:52:11 2009
>>> @@ -3202,6 +3202,19 @@
>>>                          X, DAG.getConstant(Mask, VT));
>>>     }
>>>
>>> +  // Fold (zext (and x, cst)) ->   (and (zext x), cst)
>>> +  if (N0.getOpcode() == ISD::AND&&
>>> +      N0.getOperand(1).getOpcode() == ISD::Constant&&
>>> +      N0.getOperand(0).getOpcode() != ISD::TRUNCATE&&
>>> +      N0.getOperand(0).hasOneUse()) {
>>> +    APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
>>> +    Mask.zext(VT.getSizeInBits());
>>> +    return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
>>> +                       DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
>>> +                                   N0.getOperand(0)),
>>> +                       DAG.getConstant(Mask, VT));
>>> +  }
>>> +
>>>     // fold (zext (load x)) ->   (zext (truncate (zextload x)))
>>>     if (ISD::isNON_EXTLoad(N0.getNode())&&
>>>         ((!LegalOperations&&   !cast<LoadSDNode>(N0)->isVolatile()) ||
>>>
>>> Modified: llvm/trunk/test/CodeGen/CellSPU/and_ops.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/and_ops.ll?rev=91380&r1=91379&r2=91380&view=diff
>>>
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/CellSPU/and_ops.ll (original)
>>> +++ llvm/trunk/test/CodeGen/CellSPU/and_ops.ll Mon Dec 14 18:52:11 2009
>>> @@ -1,9 +1,9 @@
>>>   ; RUN: llc<   %s -march=cellspu>   %t1.s
>>> -; RUN: grep and    %t1.s | count 234
>>> +; RUN: grep and    %t1.s | count 230
>>>   ; RUN: grep andc   %t1.s | count 85
>>> -; RUN: grep andi   %t1.s | count 37
>>> -; RUN: grep andhi  %t1.s | count 30
>>> -; RUN: grep andbi  %t1.s | count 4
>>> +; RUN: grep andi   %t1.s | count 39
>>> +; RUN: grep andhi  %t1.s | count 28
>>> +; RUN: grep andbi  %t1.s | count 2
>>>
>>>   target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
>>>   target triple = "spu"
>>>
>>>
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>>
>
>