[llvm-commits] [llvm] r91378 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/setcc.ll test/CodeGen/X86/zext-shl.ll

[Nick Lewycky]

Evan Cheng wrote:
> Author: evancheng
> Date: Mon Dec 14 18:41:36 2009
> New Revision: 91378
>
> URL: http://llvm.org/viewvc/llvm-project?rev=91378&view=rev
> Log:
> Propagate zest through logical shift.

Evan, should instcombine be doing this?

>
> Added:
>      llvm/trunk/test/CodeGen/X86/setcc.ll
>      llvm/trunk/test/CodeGen/X86/zext-shl.ll
> Modified:
>      llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=91378&r1=91377&r2=91378&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Dec 14 18:41:36 2009
> @@ -3278,6 +3278,16 @@
>       if (SCC.getNode()) return SCC;
>     }
>
> +  // (zext (shl (zext x), y)) ->  (shl (zext x), (zext y))
> +  if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL)&&
> +      N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND&&
> +      N0.hasOneUse()) {
> +    DebugLoc dl = N->getDebugLoc();
> +    return DAG.getNode(N0.getOpcode(), dl, VT,
> +                       DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),
> +                       DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(1)));
> +  }
> +
>     return SDValue();
>   }
>
>
> Added: llvm/trunk/test/CodeGen/X86/setcc.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setcc.ll?rev=91378&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/setcc.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/setcc.ll Mon Dec 14 18:41:36 2009
> @@ -0,0 +1,13 @@
> +; RUN: llc<  %s -mtriple=x86_64-apple-darwin | FileCheck %s
> +
> +define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
> +entry:
> +; CHECK: t1:
> +; CHECK: seta %al
> +; CHECK: movzbl %al, %eax
> +; CHECK: shll $5, %eax
> +  %0 = icmp ugt i16 %x, 26                        ;<i1>  [#uses=1]
> +  %iftmp.1.0 = select i1 %0, i16 32, i16 0        ;<i16>  [#uses=1]
> +  ret i16 %iftmp.1.0
> +}
> +
>
> Added: llvm/trunk/test/CodeGen/X86/zext-shl.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/zext-shl.ll?rev=91378&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/zext-shl.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/zext-shl.ll Mon Dec 14 18:41:36 2009
> @@ -0,0 +1,38 @@
> +; RUN: llc<  %s -march=x86 | FileCheck %s
> +
> +define i32 @t1(i8 zeroext %x) nounwind readnone ssp {
> +entry:
> +; CHECK: t1:
> +; CHECK: shll
> +; CHECK-NOT: movzwl
> +; CHECK: ret
> +  %0 = zext i8 %x to i16
> +  %1 = shl i16 %0, 5
> +  %2 = zext i16 %1 to i32
> +  ret i32 %2
> +}
> +
> +define i32 @t2(i8 zeroext %x) nounwind readnone ssp {
> +entry:
> +; CHECK: t2:
> +; CHECK: shrl
> +; CHECK-NOT: movzwl
> +; CHECK: ret
> +  %0 = zext i8 %x to i16
> +  %1 = lshr i16 %0, 3
> +  %2 = zext i16 %1 to i32
> +  ret i32 %2
> +}
> +
> +define i32 @t3(i8 zeroext %x, i8 zeroext %y) nounwind readnone ssp {
> +entry:
> +; CHECK: t3:
> +; CHECK: shll
> +; CHECK-NOT: movzwl
> +; CHECK: ret
> +  %0 = zext i8 %x to i16
> +  %1 = zext i8 %y to i16
> +  %2 = shl i16 %0, %1
> +  %3 = zext i16 %2 to i32
> +  ret i32 %3
> +}
>
>
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