[llvm-commits] [llvm] r91399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/zext-shl.ll

[Evan Cheng]

Author: evancheng
Date: Mon Dec 14 21:00:32 2009
New Revision: 91399

URL: http://llvm.org/viewvc/llvm-project?rev=91399&view=rev
Log:
Make 91378 more conservative.
1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest.
2. If the shift is a left shift, make sure the original shift cannot shift out bits.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/zext-shl.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=91399&r1=91398&r2=91399&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Dec 14 21:00:32 2009
@@ -3291,10 +3291,20 @@
     if (SCC.getNode()) return SCC;
   }
 
-  // (zext (shl (zext x), y)) -> (shl (zext x), (zext y))
+  // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
   if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
+      isa<ConstantSDNode>(N0.getOperand(1)) &&
       N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
       N0.hasOneUse()) {
+    if (N0.getOpcode() == ISD::SHL) {
+      // If the original shl may be shifting out bits, do not perform this
+      // transformation.
+      unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
+      unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() -
+        N0.getOperand(0).getOperand(0).getValueType().getSizeInBits();
+      if (ShAmt > KnownZeroBits)
+        return SDValue();
+    }
     DebugLoc dl = N->getDebugLoc();
     return DAG.getNode(N0.getOpcode(), dl, VT,
                        DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),

Modified: llvm/trunk/test/CodeGen/X86/zext-shl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/zext-shl.ll?rev=91399&r1=91398&r2=91399&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/zext-shl.ll (original)
+++ llvm/trunk/test/CodeGen/X86/zext-shl.ll Mon Dec 14 21:00:32 2009
@@ -23,16 +23,3 @@
   %2 = zext i16 %1 to i32
   ret i32 %2
 }
-
-define i32 @t3(i8 zeroext %x, i8 zeroext %y) nounwind readnone ssp {
-entry:
-; CHECK: t3:
-; CHECK: shll
-; CHECK-NOT: movzwl
-; CHECK: ret
-  %0 = zext i8 %x to i16
-  %1 = zext i8 %y to i16
-  %2 = shl i16 %0, %1
-  %3 = zext i16 %2 to i32
-  ret i32 %3
-}