[llvm-commits] [llvm] r91378 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/setcc.ll test/CodeGen/X86/zext-shl.ll

[Evan Cheng]

On Dec 14, 2009, at 5:05 PM, Bill Wendling wrote:

> On Dec 14, 2009, at 4:41 PM, Evan Cheng wrote:
> 
>> Author: evancheng
>> Date: Mon Dec 14 18:41:36 2009
>> New Revision: 91378
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=91378&view=rev
>> Log:
>> Propagate zest through logical shift.
>> 
>> Added:
>>   llvm/trunk/test/CodeGen/X86/setcc.ll
>>   llvm/trunk/test/CodeGen/X86/zext-shl.ll
>> Modified:
>>   llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> 
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=91378&r1=91377&r2=91378&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Dec 14 18:41:36 2009
>> @@ -3278,6 +3278,16 @@
>>    if (SCC.getNode()) return SCC;
>>  }
>> 
>> +  // (zext (shl (zext x), y)) -> (shl (zext x), (zext y))
>> +  if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
>> +      N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
> 
> Is it necessary that op 0 be zext?

Not necessary, but more likely. I can change it. (After I figure out which of my patches broke self-host).

Evan

> 
> -bw
>