[llvm-commits] [llvm] r91371 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

[Jim Grosbach]

Author: grosbach
Date: Mon Dec 14 18:12:35 2009
New Revision: 91371

URL: http://llvm.org/viewvc/llvm-project?rev=91371&view=rev
Log:
nand atomic requires opposite operand ordering

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=91371&r1=91370&r2=91371&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Dec 14 18:12:35 2009
@@ -3190,9 +3190,15 @@
   //   fallthrough --> exitMBB
   BB = loopMBB;
   AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
-  if (BinOpcode)
-    AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
-                   addReg(dest).addReg(incr)).addReg(0);
+  if (BinOpcode) {
+    // operand order needs to go the other way for NAND
+    if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
+      AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
+                     addReg(incr).addReg(dest)).addReg(0);
+    else
+      AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
+                     addReg(dest).addReg(incr)).addReg(0);
+  }
 
   AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
                  .addReg(ptr));