[llvm-commits] [PATCH] More Spill Annotations

[David Greene]

On Tuesday 24 November 2009 13:59, Evan Cheng wrote:

> > Yes, that would be cool.  I have wanted type information at the
> > MachineInstr level for some time now.  Do you imagine extending the
> > Instruction and Operand classes in Target.td and then having TableGen
> > fill in those bits?
>
> Only on instruction level, not at the operand level. Also note the
> information is imprecise. Now that I think about it, I am not sure adding
> ValueType to TargetInstrDesc makes sense since it would be a many (types)
> to one mapping. But perhaps properties like bitwidth, isVector make sense.
>
> I don't think we need to add anything to Target.td. We just need to enhance
> TargetInstrDesc and have InstrInfoEmitter fill in the information.

I think we need to add a flag to Target.td to override TableGen's inference
of "isVector."  For example:

let isVector = 0 in
def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
                         "cvtss2si\t{$src, $dst|$dst, $src}",
                         [(set GR32:$dst, (int_x86_sse_cvtss2si VR128$src))]>;

                          -Dave