[llvm-commits] [llvm] r89693 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td

[Johnny Chen]

Author: johnny
Date: Mon Nov 23 14:09:13 2009
New Revision: 89693

URL: http://llvm.org/viewvc/llvm-project?rev=89693&view=rev
Log:
Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify
{?,?,?,?} as op11_8 for VEXTd and VEXTq.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=89693&r1=89692&r2=89693&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Nov 23 14:09:13 2009
@@ -1324,20 +1324,6 @@
   let Inst{4} = op4;
 }
 
-// NEON 3 vector register with immediate.  This is only used for VEXT where
-// op11_8 represents the starting byte index of the extracted result in the
-// concatenation of the operands and is left unspecified.
-class N3VImm<bit op24, bit op23, bits<2> op21_20, bit op6, bit op4,
-             dag oops, dag iops, InstrItinClass itin,
-             string opc, string asm, string cstr, list<dag> pattern>
-  : NDataI<oops, iops, itin, opc, asm, cstr, pattern> {
-  let Inst{24} = op24;
-  let Inst{23} = op23;
-  let Inst{21-20} = op21_20;
-  let Inst{6} = op6;
-  let Inst{4} = op4;
-}
-
 // NEON VMOVs between scalar and core registers.
 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
                dag oops, dag iops, Format f, InstrItinClass itin,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=89693&r1=89692&r2=89693&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 23 14:09:13 2009
@@ -2864,18 +2864,18 @@
 //   VEXT     : Vector Extract
 
 class VEXTd<string OpcodeStr, ValueType Ty>
-  : N3VImm<0,1,0b11,0,0, (outs DPR:$dst),
-           (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
-           OpcodeStr, "\t$dst, $lhs, $rhs, $index", "",
-           [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
-                                         (Ty DPR:$rhs), imm:$index)))]>;
+  : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
+        (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
+        OpcodeStr, "\t$dst, $lhs, $rhs, $index", "",
+        [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
+                                      (Ty DPR:$rhs), imm:$index)))]>;
 
 class VEXTq<string OpcodeStr, ValueType Ty>
-  : N3VImm<0,1,0b11,1,0, (outs QPR:$dst),
-           (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
-           OpcodeStr, "\t$dst, $lhs, $rhs, $index", "",
-           [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
-                                         (Ty QPR:$rhs), imm:$index)))]>;
+  : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
+        (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
+        OpcodeStr, "\t$dst, $lhs, $rhs, $index", "",
+        [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
+                                      (Ty QPR:$rhs), imm:$index)))]>;
 
 def VEXTd8  : VEXTd<"vext.8",  v8i8>;
 def VEXTd16 : VEXTd<"vext.16", v4i16>;