[llvm-commits] [llvm] r89377 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td
Bob Wilson
bob.wilson at apple.com
Thu Nov 19 11:42:40 PST 2009
This is fine for now. Is there any reason why we can't revert it (and
similar changes that went in a while back) once pr5470 is fixed? We
should be able to specify that some of the opcode bits are undefined
without having to define separate instruction classes.
I will try to fix that PR asap.
On Nov 19, 2009, at 11:20 AM, Johnny Chen wrote:
> Author: johnny
> Date: Thu Nov 19 13:20:17 2009
> New Revision: 89377
>
> URL: http://llvm.org/viewvc/llvm-project?rev=89377&view=rev
> Log:
> Added NLdStLN which is similar to NLdSt with the exception that
> op7_4 is not
> fully specified at this level. Subclasses of NLdStLN can specify
> selective
> bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN*
> inside
> ARMInstrNEON.td.
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=89377&r1=89376&r2=89377&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Nov 19 13:20:17
> 2009
> @@ -1245,6 +1245,17 @@
> let Inst{7-4} = op7_4;
> }
>
> +// With selective bit(s) from op7_4 specified by subclasses.
> +class NLdStLN<bit op23, bits<2> op21_20, bits<4> op11_8,
> + dag oops, dag iops, InstrItinClass itin,
> + string asm, string cstr, list<dag> pattern>
> + : NeonI<oops, iops, AddrMode6, IndexModeNone, itin, asm, cstr,
> pattern> {
> + let Inst{31-24} = 0b11110100;
> + let Inst{23} = op23;
> + let Inst{21-20} = op21_20;
> + let Inst{11-8} = op11_8;
> +}
> +
> class NDataI<dag oops, dag iops, InstrItinClass itin,
> string asm, string cstr, list<dag> pattern>
> : NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, asm, cstr,
> pattern> {
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=89377&r1=89376&r2=89377&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Nov 19 13:20:17 2009
> @@ -280,66 +280,107 @@
>
> // VLD2LN : Vector Load (single 2-element structure to one lane)
> class VLD2LN<bits<4> op11_8, string OpcodeStr>
> - : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2),
> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:
> $lane),
> - IIC_VLD2,
> - !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\},
> $addr"),
> - "$src1 = $dst1, $src2 = $dst2", []>;
> + : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2),
> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:
> $lane),
> + IIC_VLD2,
> + !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\
> \}, $addr"),
> + "$src1 = $dst1, $src2 = $dst2", []>;
>
> +// vld2 to single-spaced registers.
> def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">;
> -def VLD2LNd16 : VLD2LN<0b0101, "vld2.16">;
> -def VLD2LNd32 : VLD2LN<0b1001, "vld2.32">;
> +def VLD2LNd16 : VLD2LN<0b0101, "vld2.16"> {
> + let Inst{5} = 0;
> +}
> +def VLD2LNd32 : VLD2LN<0b1001, "vld2.32"> {
> + let Inst{6} = 0;
> +}
>
> // vld2 to double-spaced even registers.
> -def VLD2LNq16a: VLD2LN<0b0101, "vld2.16">;
> -def VLD2LNq32a: VLD2LN<0b1001, "vld2.32">;
> +def VLD2LNq16a: VLD2LN<0b0101, "vld2.16"> {
> + let Inst{5} = 1;
> +}
> +def VLD2LNq32a: VLD2LN<0b1001, "vld2.32"> {
> + let Inst{6} = 1;
> +}
>
> // vld2 to double-spaced odd registers.
> -def VLD2LNq16b: VLD2LN<0b0101, "vld2.16">;
> -def VLD2LNq32b: VLD2LN<0b1001, "vld2.32">;
> +def VLD2LNq16b: VLD2LN<0b0101, "vld2.16"> {
> + let Inst{5} = 1;
> +}
> +def VLD2LNq32b: VLD2LN<0b1001, "vld2.32"> {
> + let Inst{6} = 1;
> +}
>
> // VLD3LN : Vector Load (single 3-element structure to one lane)
> class VLD3LN<bits<4> op11_8, string OpcodeStr>
> - : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2, DPR:
> $dst3),
> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
> - nohash_imm:$lane), IIC_VLD3,
> - !strconcat(OpcodeStr,
> - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
> - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
> -
> -def VLD3LNd8 : VLD3LN<0b0010, "vld3.8">;
> -def VLD3LNd16 : VLD3LN<0b0110, "vld3.16">;
> -def VLD3LNd32 : VLD3LN<0b1010, "vld3.32">;
> + : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
> + nohash_imm:$lane), IIC_VLD3,
> + !strconcat(OpcodeStr,
> + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
> + "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
> +
> +// vld3 to single-spaced registers.
> +def VLD3LNd8 : VLD3LN<0b0010, "vld3.8"> {
> + let Inst{4} = 0;
> +}
> +def VLD3LNd16 : VLD3LN<0b0110, "vld3.16"> {
> + let Inst{5-4} = 0b00;
> +}
> +def VLD3LNd32 : VLD3LN<0b1010, "vld3.32"> {
> + let Inst{6-4} = 0b000;
> +}
>
> // vld3 to double-spaced even registers.
> -def VLD3LNq16a: VLD3LN<0b0110, "vld3.16">;
> -def VLD3LNq32a: VLD3LN<0b1010, "vld3.32">;
> +def VLD3LNq16a: VLD3LN<0b0110, "vld3.16"> {
> + let Inst{5-4} = 0b10;
> +}
> +def VLD3LNq32a: VLD3LN<0b1010, "vld3.32"> {
> + let Inst{6-4} = 0b100;
> +}
>
> // vld3 to double-spaced odd registers.
> -def VLD3LNq16b: VLD3LN<0b0110, "vld3.16">;
> -def VLD3LNq32b: VLD3LN<0b1010, "vld3.32">;
> +def VLD3LNq16b: VLD3LN<0b0110, "vld3.16"> {
> + let Inst{5-4} = 0b10;
> +}
> +def VLD3LNq32b: VLD3LN<0b1010, "vld3.32"> {
> + let Inst{6-4} = 0b100;
> +}
>
> // VLD4LN : Vector Load (single 4-element structure to one lane)
> class VLD4LN<bits<4> op11_8, string OpcodeStr>
> - : NLdSt<1,0b10,op11_8,0b0000,
> - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
> DPR:$src4,
> - nohash_imm:$lane), IIC_VLD4,
> - !strconcat(OpcodeStr,
> - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\
> \}, $addr"),
> - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 =
> $dst4", []>;
> + : NLdStLN<1,0b10,op11_8,
> + (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
> DPR:$src4,
> + nohash_imm:$lane), IIC_VLD4,
> + !strconcat(OpcodeStr,
> + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4
> [$lane]\\}, $addr"),
> + "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 =
> $dst4", []>;
>
> +// vld4 to single-spaced registers.
> def VLD4LNd8 : VLD4LN<0b0011, "vld4.8">;
> -def VLD4LNd16 : VLD4LN<0b0111, "vld4.16">;
> -def VLD4LNd32 : VLD4LN<0b1011, "vld4.32">;
> +def VLD4LNd16 : VLD4LN<0b0111, "vld4.16"> {
> + let Inst{5} = 0;
> +}
> +def VLD4LNd32 : VLD4LN<0b1011, "vld4.32"> {
> + let Inst{6} = 0;
> +}
>
> // vld4 to double-spaced even registers.
> -def VLD4LNq16a: VLD4LN<0b0111, "vld4.16">;
> -def VLD4LNq32a: VLD4LN<0b1011, "vld4.32">;
> +def VLD4LNq16a: VLD4LN<0b0111, "vld4.16"> {
> + let Inst{5} = 1;
> +}
> +def VLD4LNq32a: VLD4LN<0b1011, "vld4.32"> {
> + let Inst{6} = 1;
> +}
>
> // vld4 to double-spaced odd registers.
> -def VLD4LNq16b: VLD4LN<0b0111, "vld4.16">;
> -def VLD4LNq32b: VLD4LN<0b1011, "vld4.32">;
> +def VLD4LNq16b: VLD4LN<0b0111, "vld4.16"> {
> + let Inst{5} = 1;
> +}
> +def VLD4LNq32b: VLD4LN<0b1011, "vld4.32"> {
> + let Inst{6} = 1;
> +}
>
> // VLD1DUP : Vector Load (single element to all lanes)
> // VLD2DUP : Vector Load (single 2-element structure to all lanes)
> @@ -463,64 +504,105 @@
>
> // VST2LN : Vector Store (single 2-element structure from one
> lane)
> class VST2LN<bits<4> op11_8, string OpcodeStr>
> - : NLdSt<1,0b00,op11_8,0b0000, (outs),
> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:
> $lane),
> - IIC_VST,
> - !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\},
> $addr"),
> - "", []>;
> + : NLdStLN<1,0b00,op11_8, (outs),
> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:
> $lane),
> + IIC_VST,
> + !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\
> \}, $addr"),
> + "", []>;
>
> +// vst2 to single-spaced registers.
> def VST2LNd8 : VST2LN<0b0001, "vst2.8">;
> -def VST2LNd16 : VST2LN<0b0101, "vst2.16">;
> -def VST2LNd32 : VST2LN<0b1001, "vst2.32">;
> +def VST2LNd16 : VST2LN<0b0101, "vst2.16"> {
> + let Inst{5} = 0;
> +}
> +def VST2LNd32 : VST2LN<0b1001, "vst2.32"> {
> + let Inst{6} = 0;
> +}
>
> // vst2 to double-spaced even registers.
> -def VST2LNq16a: VST2LN<0b0101, "vst2.16">;
> -def VST2LNq32a: VST2LN<0b1001, "vst2.32">;
> +def VST2LNq16a: VST2LN<0b0101, "vst2.16"> {
> + let Inst{5} = 1;
> +}
> +def VST2LNq32a: VST2LN<0b1001, "vst2.32"> {
> + let Inst{6} = 1;
> +}
>
> // vst2 to double-spaced odd registers.
> -def VST2LNq16b: VST2LN<0b0101, "vst2.16">;
> -def VST2LNq32b: VST2LN<0b1001, "vst2.32">;
> +def VST2LNq16b: VST2LN<0b0101, "vst2.16"> {
> + let Inst{5} = 1;
> +}
> +def VST2LNq32b: VST2LN<0b1001, "vst2.32"> {
> + let Inst{6} = 1;
> +}
>
> // VST3LN : Vector Store (single 3-element structure from one
> lane)
> class VST3LN<bits<4> op11_8, string OpcodeStr>
> - : NLdSt<1,0b00,op11_8,0b0000, (outs),
> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
> - nohash_imm:$lane), IIC_VST,
> - !strconcat(OpcodeStr,
> - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"),
> "", []>;
> -
> -def VST3LNd8 : VST3LN<0b0010, "vst3.8">;
> -def VST3LNd16 : VST3LN<0b0110, "vst3.16">;
> -def VST3LNd32 : VST3LN<0b1010, "vst3.32">;
> + : NLdStLN<1,0b00,op11_8, (outs),
> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
> + nohash_imm:$lane), IIC_VST,
> + !strconcat(OpcodeStr,
> + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\},
> $addr"), "", []>;
> +
> +// vst3 to single-spaced registers.
> +def VST3LNd8 : VST3LN<0b0010, "vst3.8"> {
> + let Inst{4} = 0;
> +}
> +def VST3LNd16 : VST3LN<0b0110, "vst3.16"> {
> + let Inst{5-4} = 0b00;
> +}
> +def VST3LNd32 : VST3LN<0b1010, "vst3.32"> {
> + let Inst{6-4} = 0b000;
> +}
>
> // vst3 to double-spaced even registers.
> -def VST3LNq16a: VST3LN<0b0110, "vst3.16">;
> -def VST3LNq32a: VST3LN<0b1010, "vst3.32">;
> +def VST3LNq16a: VST3LN<0b0110, "vst3.16"> {
> + let Inst{5-4} = 0b10;
> +}
> +def VST3LNq32a: VST3LN<0b1010, "vst3.32"> {
> + let Inst{6-4} = 0b100;
> +}
>
> // vst3 to double-spaced odd registers.
> -def VST3LNq16b: VST3LN<0b0110, "vst3.16">;
> -def VST3LNq32b: VST3LN<0b1010, "vst3.32">;
> +def VST3LNq16b: VST3LN<0b0110, "vst3.16"> {
> + let Inst{5-4} = 0b10;
> +}
> +def VST3LNq32b: VST3LN<0b1010, "vst3.32"> {
> + let Inst{6-4} = 0b100;
> +}
>
> // VST4LN : Vector Store (single 4-element structure from one
> lane)
> class VST4LN<bits<4> op11_8, string OpcodeStr>
> - : NLdSt<1,0b00,op11_8,0b0000, (outs),
> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
> DPR:$src4,
> - nohash_imm:$lane), IIC_VST,
> - !strconcat(OpcodeStr,
> - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\
> \}, $addr"),
> - "", []>;
> + : NLdStLN<1,0b00,op11_8, (outs),
> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
> DPR:$src4,
> + nohash_imm:$lane), IIC_VST,
> + !strconcat(OpcodeStr,
> + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4
> [$lane]\\}, $addr"),
> + "", []>;
>
> +// vst4 to single-spaced registers.
> def VST4LNd8 : VST4LN<0b0011, "vst4.8">;
> -def VST4LNd16 : VST4LN<0b0111, "vst4.16">;
> -def VST4LNd32 : VST4LN<0b1011, "vst4.32">;
> +def VST4LNd16 : VST4LN<0b0111, "vst4.16"> {
> + let Inst{5} = 0;
> +}
> +def VST4LNd32 : VST4LN<0b1011, "vst4.32"> {
> + let Inst{6} = 0;
> +}
>
> // vst4 to double-spaced even registers.
> -def VST4LNq16a: VST4LN<0b0111, "vst4.16">;
> -def VST4LNq32a: VST4LN<0b1011, "vst4.32">;
> +def VST4LNq16a: VST4LN<0b0111, "vst4.16"> {
> + let Inst{5} = 1;
> +}
> +def VST4LNq32a: VST4LN<0b1011, "vst4.32"> {
> + let Inst{6} = 1;
> +}
>
> // vst4 to double-spaced odd registers.
> -def VST4LNq16b: VST4LN<0b0111, "vst4.16">;
> -def VST4LNq32b: VST4LN<0b1011, "vst4.32">;
> +def VST4LNq16b: VST4LN<0b0111, "vst4.16"> {
> + let Inst{5} = 1;
> +}
> +def VST4LNq32b: VST4LN<0b1011, "vst4.32"> {
> + let Inst{6} = 1;
> +}
>
> } // mayStore = 1, hasExtraSrcRegAllocReq = 1
>
>
>
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