[llvm-commits] [llvm] r88874 - in /llvm/trunk: lib/Target/ARM/ARM.h lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMTargetMachine.cpp test/CodeGen/ARM/spill-q.ll test/CodeGen/Thumb2/thumb2-spill-q.ll
Chris Lattner
clattner at apple.com
Sun Nov 15 19:56:35 PST 2009
On Nov 15, 2009, at 1:45 PM, Jim Grosbach wrote:
> Author: grosbach
> Date: Sun Nov 15 15:45:34 2009
> New Revision: 88874
>
> URL: http://llvm.org/viewvc/llvm-project?rev=88874&view=rev
> Log:
> Detect need for autoalignment of the stack earlier to catch spills more
> conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
> 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
Hi Jim,
Please name the pass something less contracted (so it shows up in doxygen better without context etc). Also, does it need to be an ARM specific pass? Do other targets have this sort of issue?
-Chris
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARM.h
> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> llvm/trunk/test/CodeGen/ARM/spill-q.ll
> llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll
>
> Modified: llvm/trunk/lib/Target/ARM/ARM.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=88874&r1=88873&r2=88874&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARM.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARM.h Sun Nov 15 15:45:34 2009
> @@ -109,6 +109,7 @@
> FunctionPass *createNEONMoveFixPass();
> FunctionPass *createThumb2ITBlockPass();
> FunctionPass *createThumb2SizeReductionPass();
> +FunctionPass *createARMMaxStackAlignmentCalculatorPass();
>
> extern Target TheARMTarget, TheThumbTarget;
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=88874&r1=88873&r2=88874&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Sun Nov 15 15:45:34 2009
> @@ -1132,6 +1132,7 @@
> break;
> }
> case ARMII::AddrMode4:
> + case ARMII::AddrMode6:
> // Can't fold any offset even if it's zero.
> return false;
> case ARMII::AddrMode5: {
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=88874&r1=88873&r2=88874&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Sun Nov 15 15:45:34 2009
> @@ -1170,7 +1170,8 @@
> // as much as possible above, handle the rest, providing a register that is
> // SP+LargeImm.
> assert((Offset ||
> - (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) &&
> + (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
> + (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
> "This code isn't needed if offset already handled!");
>
> unsigned ScratchReg = 0;
> @@ -1179,7 +1180,7 @@
> ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
> unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
> if (Offset == 0)
> - // Must be addrmode4.
> + // Must be addrmode4/6.
> MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
> else {
> ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
> @@ -1462,4 +1463,46 @@
> emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
> }
>
> +namespace {
> + struct MSAC : public MachineFunctionPass {
> + static char ID;
> + MSAC() : MachineFunctionPass(&ID) {}
> +
> + virtual bool runOnMachineFunction(MachineFunction &MF) {
> + MachineFrameInfo *FFI = MF.getFrameInfo();
> + MachineRegisterInfo &RI = MF.getRegInfo();
> +
> + // Calculate max stack alignment of all already allocated stack objects.
> + unsigned MaxAlign = calculateMaxStackAlignment(FFI);
> +
> + // Be over-conservative: scan over all vreg defs and find, whether vector
> + // registers are used. If yes - there is probability, that vector register
> + // will be spilled and thus stack needs to be aligned properly.
> + for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
> + RegNum < RI.getLastVirtReg(); ++RegNum)
> + MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
> +
> + if (FFI->getMaxAlignment() == MaxAlign)
> + return false;
> +
> + FFI->setMaxAlignment(MaxAlign);
> + return true;
> + }
> +
> + virtual const char *getPassName() const {
> + return "ARM Maximal Stack Alignment Calculator";
> + }
> +
> + virtual void getAnalysisUsage(AnalysisUsage &AU) const {
> + AU.setPreservesCFG();
> + MachineFunctionPass::getAnalysisUsage(AU);
> + }
> + };
> +
> + char MSAC::ID = 0;
> +}
> +
> +FunctionPass*
> +llvm::createARMMaxStackAlignmentCalculatorPass() { return new MSAC(); }
> +
> #include "ARMGenRegisterInfo.inc"
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=88874&r1=88873&r2=88874&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Sun Nov 15 15:45:34 2009
> @@ -93,6 +93,10 @@
> if (Subtarget.hasNEON())
> PM.add(createNEONPreAllocPass());
>
> + // Calculate and set max stack object alignment early, so we can decide
> + // whether we will need stack realignment (and thus FP).
> + PM.add(createARMMaxStackAlignmentCalculatorPass());
> +
> // FIXME: temporarily disabling load / store optimization pass for Thumb1.
> if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
> PM.add(createARMLoadStoreOptimizationPass(true));
>
> Modified: llvm/trunk/test/CodeGen/ARM/spill-q.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/spill-q.ll?rev=88874&r1=88873&r2=88874&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/spill-q.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/spill-q.ll Sun Nov 15 15:45:34 2009
> @@ -11,8 +11,9 @@
>
> define arm_apcscc void @aaa(%quuz* %this, i8* %block) {
> ; CHECK: aaa:
> -; CHECK: vstmia sp
> -; CHECK: vldmia sp
> +; CHECK: bic sp, sp, #15
> +; CHECK: vst1.64 {{.*}}sp @128
> +; CHECK: vld1.64 {{.*}}sp @128
> entry:
> %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1]
> store float 6.300000e+01, float* undef, align 4
>
> Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll?rev=88874&r1=88873&r2=88874&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll (original)
> +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll Sun Nov 15 15:45:34 2009
> @@ -11,8 +11,9 @@
>
> define arm_apcscc void @aaa(%quuz* %this, i8* %block) {
> ; CHECK: aaa:
> -; CHECK: vstmia sp
> -; CHECK: vldmia sp
> +; CHECK: bic sp, sp, #15
> +; CHECK: vst1.64 {{.*}}sp @128
> +; CHECK: vld1.64 {{.*}}sp @128
> entry:
> %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1]
> store float 6.300000e+01, float* undef, align 4
>
>
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