[llvm-commits] [llvm] r88802 - in /llvm/trunk: lib/Target/XCore/XCoreISelLowering.cpp lib/Target/XCore/XCoreISelLowering.h test/CodeGen/XCore/bigstructret.ll
Richard Osborne
richard at xmos.com
Sat Nov 14 11:33:35 PST 2009
Author: friedgold
Date: Sat Nov 14 13:33:35 2009
New Revision: 88802
URL: http://llvm.org/viewvc/llvm-project?rev=88802&view=rev
Log:
Add XCore support for arbitrary-sized aggregate returns.
Added:
llvm/trunk/test/CodeGen/XCore/bigstructret.ll
Modified:
llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=88802&r1=88801&r2=88802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Sat Nov 14 13:33:35 2009
@@ -918,6 +918,17 @@
// Return Value Calling Convention Implementation
//===----------------------------------------------------------------------===//
+bool XCoreTargetLowering::
+CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<EVT> &OutTys,
+ const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
+ SelectionDAG &DAG) {
+ SmallVector<CCValAssign, 16> RVLocs;
+ CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
+ RVLocs, *DAG.getContext());
+ return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_XCore);
+}
+
SDValue
XCoreTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.h?rev=88802&r1=88801&r2=88802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.h Sat Nov 14 13:33:35 2009
@@ -159,6 +159,12 @@
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG);
+
+ virtual bool
+ CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<EVT> &OutTys,
+ const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
+ SelectionDAG &DAG);
};
}
Added: llvm/trunk/test/CodeGen/XCore/bigstructret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/bigstructret.ll?rev=88802&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/bigstructret.ll (added)
+++ llvm/trunk/test/CodeGen/XCore/bigstructret.ll Sat Nov 14 13:33:35 2009
@@ -0,0 +1,43 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+
+%0 = type { i32, i32, i32, i32 }
+%1 = type { i32, i32, i32, i32, i32 }
+
+; Structs of 4 words can be returned in registers
+define internal fastcc %0 @ReturnBigStruct() nounwind readnone {
+entry:
+ %0 = insertvalue %0 zeroinitializer, i32 12, 0
+ %1 = insertvalue %0 %0, i32 24, 1
+ %2 = insertvalue %0 %1, i32 48, 2
+ %3 = insertvalue %0 %2, i32 24601, 3
+ ret %0 %3
+}
+; CHECK: ReturnBigStruct:
+; CHECK: ldc r0, 12
+; CHECK: ldc r1, 24
+; CHECK: ldc r2, 48
+; CHECK: ldc r3, 24601
+; CHECK: retsp 0
+
+; Structs bigger than 4 words are returned via a hidden hidden sret-parameter
+define internal fastcc %1 @ReturnBigStruct2() nounwind readnone {
+entry:
+ %0 = insertvalue %1 zeroinitializer, i32 12, 0
+ %1 = insertvalue %1 %0, i32 24, 1
+ %2 = insertvalue %1 %1, i32 48, 2
+ %3 = insertvalue %1 %2, i32 24601, 3
+ %4 = insertvalue %1 %3, i32 4321, 4
+ ret %1 %4
+}
+; CHECK: ReturnBigStruct2:
+; CHECK: ldc r1, 4321
+; CHECK: stw r1, r0[4]
+; CHECK: ldc r1, 24601
+; CHECK: stw r1, r0[3]
+; CHECK: ldc r1, 48
+; CHECK: stw r1, r0[2]
+; CHECK: ldc r1, 24
+; CHECK: stw r1, r0[1]
+; CHECK: ldc r1, 12
+; CHECK: stw r1, r0[0]
+; CHECK: retsp 0
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