[llvm-commits] Question on emitLoadStoreInstruction() of ARMCodeEmitter.cpp

[Evan Cheng]

On Nov 10, 2009, at 8:52 AM, Johnny Chen wrote:

> Hi Evan,
>
> Thanks for the reply.
> But from the emitLoadStoreInstruction() code inspection, it looks  
> like it special-cases for
> operand 0 to be base_wb and operand 1 to be dst, which is not the  
> correct order.
> It should have been operand 0 as dst and operand 1 as base_wb?

I don't see it. I haven't been able to test the JIT for a long time  
but this code used to work fine. Is something broken?

Evan

>
> Johnny
>
> On Nov 9, 2009, at 10:38 PM, Evan Cheng wrote:
>
>>
>> On Nov 9, 2009, at 5:46 PM, Johnny Chen wrote:
>>
>>>
>>> Hi,
>>>
>>> I have a question wrt the following fragment of code:
>>>
>>> // Operand 0 of a pre- and post-indexed store is the address base
>>> // writeback. Skip it.
>>> bool Skipped = false;
>>> if (IsPrePost && Form == ARMII::StFrm) {
>>>  ++OpIdx;
>>>  Skipped = true;
>>> }
>>>
>>> // Set first operand
>>> if (ImplicitRd)
>>>  // Special handling for implicit use (e.g. PC).
>>>  Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
>>>             << ARMII::RegRdShift);
>>> else
>>>  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
>>>
>>> and from the Record definition of LDRB_POST:
>>>
>>> def LDRB_POST {	// Instruction InstARM I AI2ldbpo
>>> field bits<32> Inst = { ?, ?, ?, ?, 0, 1, ?, 0, ?, 1, 0,  
>>> 1, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
>>> string Namespace = "ARM";
>>> dag OutOperandList = (outs GPR:$dst, GPR:$base_wb);
>>> dag InOperandList = (ins GPR:$base, am2offset:$offset, pred:$p);
>>> string AsmString = "ldrb${p}	$dst, [$base], $offset";
>>>
>>> it looks like the processing of "address base writeback" should  
>>> happen after the processing of RegRd,
>>> if the ordering of OutOperandList followed by InOperandList is to  
>>> be observed.  Is my understanding of
>>> the ordering of the MachineOperands correct?
>>
>> Right. Defs comes first followed by uses.
>>
>>>
>>> If this is the case, then there could be some bug in the codegen  
>>> which compensates for the incorrect
>>> ordering/processing of base_writeback/dst?
>>
>> No. It's fine. The second operand is base_wb, base will be skipped.
>>
>> Evan
>>
>>>
>>> Thanks.
>>> _______________________________________________
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>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>