[llvm-commits] [llvm] r86628 - in /llvm/trunk: include/llvm/Target/TargetSubtarget.h lib/CodeGen/AggressiveAntiDepBreaker.cpp lib/CodeGen/AggressiveAntiDepBreaker.h lib/CodeGen/PostRASchedulerList.cpp lib/Target/ARM/ARMSubtarget.h lib/Target/X86/X86Subtarget.h
Chris Lattner
clattner at apple.com
Mon Nov 9 16:25:33 PST 2009
On Nov 9, 2009, at 4:15 PM, David Goodwin wrote:
> Author: david_goodwin
> Date: Mon Nov 9 18:15:47 2009
> New Revision: 86628
>
> URL: http://llvm.org/viewvc/llvm-project?rev=86628&view=rev
> Log:
> Allow targets to specify register classes whose member registers
> should not be renamed to break anti-dependencies.
I don't have anything to say about the technical merits of this patch,
but...
> +++ llvm/trunk/include/llvm/Target/TargetSubtarget.h Mon Nov 9
> 18:15:47 2009
> @@ -15,6 +15,8 @@
> #define LLVM_TARGET_TARGETSUBTARGET_H
>
> #include "llvm/Target/TargetMachine.h"
> +#include "llvm/Target/TargetRegisterInfo.h"
> +#include "llvm/ADT/SmallVector.h"
Please just forward declare what you need from these two headers
instead of #including them. Also, for APIs that take a smallvector
and fill it in, they should generally take a SmallVectorImpl<T>
instead of specifying a size (that way the client has the ability to
pick a size). You can forward declare SmallVectorImpl like this:
namespace llvm {
template <typename T> class SmallVectorImpl;
}
and move the virtual method out of line to avoid the .clear() in the
header.
Thanks David,
-Chris
>
> namespace llvm {
>
> @@ -36,6 +38,7 @@
> // AntiDepBreakMode - Type of anti-dependence breaking that should
> // be performed before post-RA scheduling.
> typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL }
> AntiDepBreakMode;
> + typedef SmallVector<TargetRegisterClass*, 4> ExcludedRCVector;
>
> virtual ~TargetSubtarget();
>
> @@ -49,8 +52,10 @@
> // scheduling and the specified optimization level meets the
> requirement
> // return true to enable post-register-allocation scheduling.
> virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
> - AntiDepBreakMode& mode) const {
> - mode = ANTIDEP_NONE;
> + AntiDepBreakMode& Mode,
> + ExcludedRCVector& ExcludedRCs)
> const {
> + Mode = ANTIDEP_NONE;
> + ExcludedRCs.clear();
> return false;
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=86628&r1=86627&r2=86628&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Mon Nov 9
> 18:15:47 2009
> @@ -99,12 +99,24 @@
>
>
> AggressiveAntiDepBreaker::
> -AggressiveAntiDepBreaker(MachineFunction& MFi) :
> +AggressiveAntiDepBreaker(MachineFunction& MFi,
> + TargetSubtarget::ExcludedRCVector&
> ExcludedRCs) :
> AntiDepBreaker(), MF(MFi),
> MRI(MF.getRegInfo()),
> TRI(MF.getTarget().getRegisterInfo()),
> AllocatableSet(TRI->getAllocatableSet(MF)),
> State(NULL), SavedState(NULL) {
> + /* Remove all registers from excluded RCs from the allocatable
> + register set. */
> + for (unsigned i = 0, e = ExcludedRCs.size(); i < e; ++i) {
> + BitVector NotRenameable = TRI->getAllocatableSet(MF,
> ExcludedRCs[i]).flip();
> + AllocatableSet &= NotRenameable;
> + }
> +
> + DEBUG(errs() << "AntiDep Renameable Registers:");
> + DEBUG(for (int r = AllocatableSet.find_first(); r != -1;
> + r = AllocatableSet.find_next(r))
> + errs() << " " << TRI->getName(r));
> }
>
> AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
>
> Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=86628&r1=86627&r2=86628&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original)
> +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Mon Nov 9
> 18:15:47 2009
> @@ -23,6 +23,7 @@
> #include "llvm/CodeGen/MachineFunction.h"
> #include "llvm/CodeGen/MachineRegisterInfo.h"
> #include "llvm/CodeGen/ScheduleDAG.h"
> +#include "llvm/Target/TargetSubtarget.h"
> #include "llvm/Target/TargetRegisterInfo.h"
> #include "llvm/ADT/BitVector.h"
> #include "llvm/ADT/SmallSet.h"
> @@ -112,7 +113,7 @@
> /// AllocatableSet - The set of allocatable registers.
> /// We'll be ignoring anti-dependencies on non-allocatable
> registers,
> /// because they may not be safe to break.
> - const BitVector AllocatableSet;
> + BitVector AllocatableSet;
>
> /// State - The state used to identify and rename anti-dependence
> /// registers.
> @@ -124,7 +125,8 @@
> AggressiveAntiDepState *SavedState;
>
> public:
> - AggressiveAntiDepBreaker(MachineFunction& MFi);
> + AggressiveAntiDepBreaker(MachineFunction& MFi,
> + TargetSubtarget::ExcludedRCVector&
> ExcludedRCs);
> ~AggressiveAntiDepBreaker();
>
> /// GetMaxTrials - As anti-dependencies are broken, additional
>
> Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=86628&r1=86627&r2=86628&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
> +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Mon Nov 9
> 18:15:47 2009
> @@ -216,13 +216,14 @@
>
> // Check for explicit enable/disable of post-ra scheduling.
> TargetSubtarget::AntiDepBreakMode AntiDepMode =
> TargetSubtarget::ANTIDEP_NONE;
> + TargetSubtarget::ExcludedRCVector ExcludedRCs;
> if (EnablePostRAScheduler.getPosition() > 0) {
> if (!EnablePostRAScheduler)
> return false;
> } else {
> // Check that post-RA scheduling is enabled for this target.
> const TargetSubtarget &ST =
> Fn.getTarget().getSubtarget<TargetSubtarget>();
> - if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode))
> + if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode,
> ExcludedRCs))
> return false;
> }
>
> @@ -243,7 +244,7 @@
> (ScheduleHazardRecognizer *)new SimpleHazardRecognizer();
> AntiDepBreaker *ADB =
> ((AntiDepMode == TargetSubtarget::ANTIDEP_ALL) ?
> - (AntiDepBreaker *)new AggressiveAntiDepBreaker(Fn) :
> + (AntiDepBreaker *)new AggressiveAntiDepBreaker(Fn,
> ExcludedRCs) :
> ((AntiDepMode == TargetSubtarget::ANTIDEP_CRITICAL) ?
> (AntiDepBreaker *)new CriticalAntiDepBreaker(Fn) : NULL));
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=86628&r1=86627&r2=86628&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Nov 9 18:15:47 2009
> @@ -17,6 +17,7 @@
> #include "llvm/Target/TargetInstrItineraries.h"
> #include "llvm/Target/TargetMachine.h"
> #include "llvm/Target/TargetSubtarget.h"
> +#include "ARMBaseRegisterInfo.h"
> #include <string>
>
> namespace llvm {
> @@ -129,8 +130,11 @@
> /// enablePostRAScheduler - True at 'More' optimization except
> /// for Thumb1.
> bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
> - TargetSubtarget::AntiDepBreakMode&
> mode) const {
> - mode = TargetSubtarget::ANTIDEP_CRITICAL;
> + TargetSubtarget::AntiDepBreakMode& Mode,
> + ExcludedRCVector& ExcludedRCs) const {
> + Mode = TargetSubtarget::ANTIDEP_CRITICAL;
> + ExcludedRCs.clear();
> + ExcludedRCs.push_back(&ARM::GPRRegClass);
> return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=86628&r1=86627&r2=86628&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon Nov 9 18:15:47 2009
> @@ -219,8 +219,10 @@
> /// enablePostRAScheduler - X86 target is enabling post-alloc
> scheduling
> /// at 'More' optimization level.
> bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
> - TargetSubtarget::AntiDepBreakMode&
> mode) const {
> - mode = TargetSubtarget::ANTIDEP_CRITICAL;
> + TargetSubtarget::AntiDepBreakMode& Mode,
> + ExcludedRCVector& ExcludedRCs) const {
> + Mode = TargetSubtarget::ANTIDEP_CRITICAL;
> + ExcludedRCs.clear();
> return OptLevel >= CodeGenOpt::Default;
> }
> };
>
>
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