[llvm-commits] [llvm] r86486 - /llvm/trunk/lib/Transforms/Scalar/ABCD.cpp

[Owen Anderson]

Author: resistor
Date: Sun Nov  8 16:36:55 2009
New Revision: 86486

URL: http://llvm.org/viewvc/llvm-project?rev=86486&view=rev
Log:
Fix an issue where the ordering of blocks within a function could lead to different constraint
graphs being produced.  The cause was that we were incorrectly marking sigma instructions as
processed after handling the sigma-specific constraints for them, potentially neglecting to
process them as normal instructions as well.

Unfortunately, the testcase that inspired this still doesn't work because of a bug in the solver,
which is next on the list to debug.

Modified:
    llvm/trunk/lib/Transforms/Scalar/ABCD.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/ABCD.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ABCD.cpp?rev=86486&r1=86485&r2=86486&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ABCD.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ABCD.cpp Sun Nov  8 16:36:55 2009
@@ -796,13 +796,15 @@
     int32_t width = cast<IntegerType>((*SIG_op_t)->getType())->getBitWidth();
     inequality_graph.addEdge(I_op, *SIG_op_t, APInt(width, 0), true);
     inequality_graph.addEdge(*SIG_op_t, I_op, APInt(width, 0), false);
-    created.insert(*SIG_op_t);
+    if (created.insert(*SIG_op_t))
+      createConstraintPHINode(cast<PHINode>(*SIG_op_t));
   }
   if (*SIG_op_f) {
     int32_t width = cast<IntegerType>((*SIG_op_f)->getType())->getBitWidth();
     inequality_graph.addEdge(I_op, *SIG_op_f, APInt(width, 0), true);
     inequality_graph.addEdge(*SIG_op_f, I_op, APInt(width, 0), false);
-    created.insert(*SIG_op_f);
+    if (created.insert(*SIG_op_f))
+      createConstraintPHINode(cast<PHINode>(*SIG_op_f));
   }
 }