[llvm-commits] [llvm] r86471 - in /llvm/trunk: lib/Target/MSP430/MSP430InstrInfo.td test/CodeGen/MSP430/Inst16mr.ll test/CodeGen/MSP430/Inst16rm.ll test/CodeGen/MSP430/Inst16rr.ll test/CodeGen/MSP430/Inst8mr.ll test/CodeGen/MSP430/Inst8rm.ll test/CodeGen/MSP430/Inst8rr.ll
Anton Korobeynikov
asl at math.spbu.ru
Sun Nov 8 07:33:12 PST 2009
Author: asl
Date: Sun Nov 8 09:33:12 2009
New Revision: 86471
URL: http://llvm.org/viewvc/llvm-project?rev=86471&view=rev
Log:
Add and-not (bic) patterns. Based heavily on patch by Brian Lucas!
Modified:
llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
llvm/trunk/test/CodeGen/MSP430/Inst16mr.ll
llvm/trunk/test/CodeGen/MSP430/Inst16rm.ll
llvm/trunk/test/CodeGen/MSP430/Inst16rr.ll
llvm/trunk/test/CodeGen/MSP430/Inst8mr.ll
llvm/trunk/test/CodeGen/MSP430/Inst8rm.ll
llvm/trunk/test/CodeGen/MSP430/Inst8rr.ll
Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td?rev=86471&r1=86470&r2=86471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td Sun Nov 8 09:33:12 2009
@@ -462,7 +462,6 @@
(implicit SRW)]>;
}
-
let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"bis.b\t{$src2, $dst}",
@@ -519,6 +518,37 @@
(i16 (load addr:$src))), addr:$dst)]>;
}
+// bic does not modify condition codes
+def BIC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
+ "bic.b\t{$src2, $dst}",
+ [(set GR8:$dst, (and GR8:$src1, (not GR8:$src2)))]>;
+def BIC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "bic.w\t{$src2, $dst}",
+ [(set GR16:$dst, (and GR16:$src1, (not GR16:$src2)))]>;
+
+def BIC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
+ "bic.b\t{$src2, $dst}",
+ [(set GR8:$dst, (and GR8:$src1, (not (i8 (load addr:$src2)))))]>;
+def BIC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
+ "bic.w\t{$src2, $dst}",
+ [(set GR16:$dst, (and GR16:$src1, (not (i16 (load addr:$src2)))))]>;
+
+let isTwoAddress = 0 in {
+def BIC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
+ "bic.b\t{$src, $dst}",
+ [(store (and (load addr:$dst), (not GR8:$src)), addr:$dst)]>;
+def BIC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
+ "bic.w\t{$src, $dst}",
+ [(store (and (load addr:$dst), (not GR16:$src)), addr:$dst)]>;
+
+def BIC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
+ "bic.b\t{$src, $dst}",
+ [(store (and (load addr:$dst), (not (i8 (load addr:$src)))), addr:$dst)]>;
+def BIC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
+ "bic.w\t{$src, $dst}",
+ [(store (and (load addr:$dst), (not (i16 (load addr:$src)))), addr:$dst)]>;
+}
+
let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"xor.b\t{$src2, $dst}",
Modified: llvm/trunk/test/CodeGen/MSP430/Inst16mr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16mr.ll?rev=86471&r1=86470&r2=86471&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst16mr.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst16mr.ll Sun Nov 8 09:33:12 2009
@@ -37,6 +37,16 @@
ret void
}
+define void @bic(i16 zeroext %m) nounwind {
+; CHECK: bic:
+; CHECK: bic.w r15, &foo
+ %1 = xor i16 %m, -1
+ %2 = load i16* @foo
+ %3 = and i16 %2, %1
+ store i16 %3, i16* @foo
+ ret void
+}
+
define void @xor(i16 %a) nounwind {
; CHECK: xor:
; CHECK: xor.w r15, &foo
Modified: llvm/trunk/test/CodeGen/MSP430/Inst16rm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16rm.ll?rev=86471&r1=86470&r2=86471&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst16rm.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst16rm.ll Sun Nov 8 09:33:12 2009
@@ -19,7 +19,6 @@
ret i16 %2
}
-
define i16 @bis(i16 %a) nounwind {
; CHECK: bis:
; CHECK: bis.w &foo, r15
@@ -28,6 +27,15 @@
ret i16 %2
}
+define i16 @bic(i16 %a) nounwind {
+; CHECK: bic:
+; CHECK: bic.w &foo, r15
+ %1 = load i16* @foo
+ %2 = xor i16 %1, -1
+ %3 = and i16 %a, %2
+ ret i16 %3
+}
+
define i16 @xor(i16 %a) nounwind {
; CHECK: xor:
; CHECK: xor.w &foo, r15
Modified: llvm/trunk/test/CodeGen/MSP430/Inst16rr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16rr.ll?rev=86471&r1=86470&r2=86471&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst16rr.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst16rr.ll Sun Nov 8 09:33:12 2009
@@ -29,6 +29,14 @@
ret i16 %1
}
+define i16 @bic(i16 %a, i16 %b) nounwind {
+; CHECK: bic:
+; CHECK: bic.w r14, r15
+ %1 = xor i16 %b, -1
+ %2 = and i16 %a, %1
+ ret i16 %2
+}
+
define i16 @xor(i16 %a, i16 %b) nounwind {
; CHECK: xor:
; CHECK: xor.w r14, r15
Modified: llvm/trunk/test/CodeGen/MSP430/Inst8mr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst8mr.ll?rev=86471&r1=86470&r2=86471&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst8mr.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst8mr.ll Sun Nov 8 09:33:12 2009
@@ -37,6 +37,16 @@
ret void
}
+define void @bic(i8 zeroext %m) nounwind {
+; CHECK: bic:
+; CHECK: bic.b r15, &foo
+ %1 = xor i8 %m, -1
+ %2 = load i8* @foo
+ %3 = and i8 %2, %1
+ store i8 %3, i8* @foo
+ ret void
+}
+
define void @xor(i8 %a) nounwind {
; CHECK: xor:
; CHECK: xor.b r15, &foo
Modified: llvm/trunk/test/CodeGen/MSP430/Inst8rm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst8rm.ll?rev=86471&r1=86470&r2=86471&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst8rm.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst8rm.ll Sun Nov 8 09:33:12 2009
@@ -19,7 +19,6 @@
ret i8 %2
}
-
define i8 @bis(i8 %a) nounwind {
; CHECK: bis:
; CHECK: bis.b &foo, r15
@@ -28,6 +27,15 @@
ret i8 %2
}
+define i8 @bic(i8 %a) nounwind {
+; CHECK: bic:
+; CHECK: bic.b &foo, r15
+ %1 = load i8* @foo
+ %2 = xor i8 %1, -1
+ %3 = and i8 %a, %2
+ ret i8 %3
+}
+
define i8 @xor(i8 %a) nounwind {
; CHECK: xor:
; CHECK: xor.b &foo, r15
Modified: llvm/trunk/test/CodeGen/MSP430/Inst8rr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst8rr.ll?rev=86471&r1=86470&r2=86471&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst8rr.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst8rr.ll Sun Nov 8 09:33:12 2009
@@ -29,6 +29,14 @@
ret i8 %1
}
+define i8 @bic(i8 %a, i8 %b) nounwind {
+; CHECK: bic:
+; CHECK: bic.b r14, r15
+ %1 = xor i8 %b, -1
+ %2 = and i8 %a, %1
+ ret i8 %2
+}
+
define i8 @xor(i8 %a, i8 %b) nounwind {
; CHECK: xor:
; CHECK: xor.w r14, r15
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