[llvm-commits] [llvm] r86319 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Johnny Chen
johnny.chen at apple.com
Fri Nov 6 16:54:36 PST 2009
Author: johnny
Date: Fri Nov 6 18:54:36 2009
New Revision: 86319
URL: http://llvm.org/viewvc/llvm-project?rev=86319&view=rev
Log:
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=86319&r1=86318&r2=86319&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Nov 6 18:54:36 2009
@@ -377,15 +377,13 @@
def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
IIC_iALUr, opc, "\t$dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
- let Inst{4} = 0;
+ let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
let isCommutable = Commutable;
}
def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALUsr, opc, "\t$dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
- let Inst{4} = 1;
- let Inst{7} = 0;
let Inst{25} = 0;
}
}
@@ -405,15 +403,13 @@
IIC_iALUr, opc, "s\t$dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
let isCommutable = Commutable;
- let Inst{4} = 0;
+ let Inst{11-4} = 0b00000000;
let Inst{20} = 1;
let Inst{25} = 0;
}
def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALUsr, opc, "s\t$dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
- let Inst{4} = 1;
- let Inst{7} = 0;
let Inst{20} = 1;
let Inst{25} = 0;
}
@@ -435,7 +431,7 @@
def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
opc, "\t$a, $b",
[(opnode GPR:$a, GPR:$b)]> {
- let Inst{4} = 0;
+ let Inst{11-4} = 0b00000000;
let Inst{20} = 1;
let Inst{25} = 0;
let isCommutable = Commutable;
@@ -443,8 +439,6 @@
def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
opc, "\t$a, $b",
[(opnode GPR:$a, so_reg:$b)]> {
- let Inst{4} = 1;
- let Inst{7} = 0;
let Inst{20} = 1;
let Inst{25} = 0;
}
@@ -501,15 +495,13 @@
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
Requires<[IsARM, CarryDefIsUnused]> {
let isCommutable = Commutable;
- let Inst{4} = 0;
+ let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
}
def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
Requires<[IsARM, CarryDefIsUnused]> {
- let Inst{4} = 1;
- let Inst{7} = 0;
let Inst{25} = 0;
}
// Carry setting variants
@@ -526,7 +518,7 @@
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
Requires<[IsARM, CarryDefIsUsed]> {
let Defs = [CPSR];
- let Inst{4} = 0;
+ let Inst{11-4} = 0b00000000;
let Inst{20} = 1;
let Inst{25} = 0;
}
@@ -535,8 +527,6 @@
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
Requires<[IsARM, CarryDefIsUsed]> {
let Defs = [CPSR];
- let Inst{4} = 1;
- let Inst{7} = 0;
let Inst{20} = 1;
let Inst{25} = 0;
}
@@ -963,15 +953,13 @@
let neverHasSideEffects = 1 in
def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
"mov", "\t$dst, $src", []>, UnaryDP {
- let Inst{4} = 0;
+ let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
}
def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
DPSoRegFrm, IIC_iMOVsr,
"mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
- let Inst{4} = 1;
- let Inst{7} = 0;
let Inst{25} = 0;
}
@@ -1115,8 +1103,6 @@
def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALUsr, "rsb", "\t$dst, $a, $b",
[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
- let Inst{4} = 1;
- let Inst{7} = 0;
let Inst{25} = 0;
}
@@ -1131,8 +1117,6 @@
def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALUsr, "rsb", "s\t$dst, $a, $b",
[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
- let Inst{4} = 1;
- let Inst{7} = 0;
let Inst{20} = 1;
let Inst{25} = 0;
}
@@ -1149,8 +1133,6 @@
DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
Requires<[IsARM, CarryDefIsUnused]> {
- let Inst{4} = 1;
- let Inst{7} = 0;
let Inst{25} = 0;
}
}
@@ -1168,8 +1150,6 @@
DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
Requires<[IsARM, CarryDefIsUnused]> {
- let Inst{4} = 1;
- let Inst{7} = 0;
let Inst{20} = 1;
let Inst{25} = 0;
}
@@ -1216,14 +1196,11 @@
def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
"mvn", "\t$dst, $src",
[(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
- let Inst{4} = 0;
+ let Inst{11-4} = 0b00000000;
}
def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
IIC_iMOVsr, "mvn", "\t$dst, $src",
- [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
- let Inst{4} = 1;
- let Inst{7} = 0;
-}
+ [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
IIC_iMOVi, "mvn", "\t$dst, $imm",
@@ -1536,7 +1513,7 @@
IIC_iCMOVr, "mov", "\t$dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">, UnaryDP {
- let Inst{4} = 0;
+ let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
}
@@ -1545,8 +1522,6 @@
"mov", "\t$dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">, UnaryDP {
- let Inst{4} = 1;
- let Inst{7} = 0;
let Inst{25} = 0;
}
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