[llvm-commits] [llvm] r85764 - in /llvm/trunk/lib/Target/ARM: ARM.td ARMBaseInstrInfo.cpp ARMBaseInstrInfo.h ARMInstrFormats.td ARMInstrInfo.cpp ARMInstrInfo.h Thumb1InstrInfo.cpp Thumb2InstrInfo.cpp
Evan Cheng
evan.cheng at apple.com
Sun Nov 1 18:52:29 PST 2009
Anton,
I don't think this patch is the right way to go. You are making
ARMBaseInstrInfo::copyRegToReg() extremely expensive. When DestRC ==
ARM::DPRRegisterClass it scans from the insertion point towards the
top of the MBB to find the definition. There are two issues:
1. When the register is virtual, it could have used
machineregisterinfo to find the def. It would have been much faster.
2. When the register is physical it can scan all the way to the top of
the MBB, that's extremely expensive.
Evan
On Nov 1, 2009, at 6:04 PM, Evan Cheng wrote:
> Did you test this with llvm test suite? I am seeing lots of crashes in
> ARMBaseInstrInfo::copyRegToReg.
>
> Evan
>
> On Nov 1, 2009, at 4:10 PM, Anton Korobeynikov wrote:
>
>> Author: asl
>> Date: Sun Nov 1 18:10:38 2009
>> New Revision: 85764
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=85764&view=rev
>> Log:
>> Use NEON reg-reg moves, where profitable. This reduces "domain-
>> cross" stalls, when we used to mix vfp and neon code (the former
>> were used for reg-reg moves)
>>
>> Modified:
>> llvm/trunk/lib/Target/ARM/ARM.td
>> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
>> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
>> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>> llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
>> llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
>> llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
>> llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARM.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=85764&r1=85763&r2=85764&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARM.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARM.td Sun Nov 1 18:10:38 2009
>> @@ -125,12 +125,16 @@
>> "SizeFlag",
>> "IndexModeBits",
>> "Form",
>> - "isUnaryDataProc"];
>> + "isUnaryDataProc",
>> + "canXformTo16Bit",
>> + "Dom"];
>> let TSFlagsShifts = [0,
>> 4,
>> 7,
>> 9,
>> - 15];
>> + 15,
>> + 16,
>> + 17];
>> }
>>
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=85764&r1=85763&r2=85764&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Sun Nov 1
>> 18:10:38 2009
>> @@ -16,15 +16,18 @@
>> #include "ARMAddressingModes.h"
>> #include "ARMGenInstrInfo.inc"
>> #include "ARMMachineFunctionInfo.h"
>> +#include "ARMRegisterInfo.h"
>> #include "llvm/ADT/STLExtras.h"
>> #include "llvm/CodeGen/LiveVariables.h"
>> #include "llvm/CodeGen/MachineFrameInfo.h"
>> #include "llvm/CodeGen/MachineInstrBuilder.h"
>> #include "llvm/CodeGen/MachineJumpTableInfo.h"
>> #include "llvm/CodeGen/MachineMemOperand.h"
>> +#include "llvm/CodeGen/MachineRegisterInfo.h"
>> #include "llvm/CodeGen/PseudoSourceValue.h"
>> #include "llvm/MC/MCAsmInfo.h"
>> #include "llvm/Support/CommandLine.h"
>> +#include "llvm/Support/Debug.h"
>> #include "llvm/Support/ErrorHandling.h"
>> using namespace llvm;
>>
>> @@ -32,8 +35,9 @@
>> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
>> cl::desc("Enable ARM 2-addr to 3-addr conv"));
>>
>> -ARMBaseInstrInfo::ARMBaseInstrInfo()
>> - : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
>> +ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
>> + : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
>> + Subtarget(STI) {
>> }
>>
>> MachineInstr *
>> @@ -504,7 +508,7 @@
>> case ARM::FCPYS:
>> case ARM::FCPYD:
>> case ARM::VMOVD:
>> - case ARM::VMOVQ: {
>> + case ARM::VMOVQ: {
>> SrcReg = MI.getOperand(1).getReg();
>> DstReg = MI.getOperand(0).getReg();
>> return true;
>> @@ -647,11 +651,45 @@
>> } else if (DestRC == ARM::SPRRegisterClass) {
>> AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
>> .addReg(SrcReg));
>> - } else if ((DestRC == ARM::DPRRegisterClass) ||
>> - (DestRC == ARM::DPR_VFP2RegisterClass) ||
>> - (DestRC == ARM::DPR_8RegisterClass)) {
>> - AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
>> - .addReg(SrcReg));
>> + } else if (DestRC == ARM::DPR_VFP2RegisterClass ||
>> + DestRC == ARM::DPR_8RegisterClass ||
>> + SrcRC == ARM::DPR_VFP2RegisterClass ||
>> + SrcRC == ARM::DPR_8RegisterClass) {
>> + // Always use neon reg-reg move if source or dest is NEON-only
>> regclass.
>> + BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg).addReg(SrcReg);
>> + } else if (DestRC == ARM::DPRRegisterClass) {
>> + const ARMBaseRegisterInfo* TRI = &getRegisterInfo();
>> +
>> + // Find the Machine Instruction which defines SrcReg.
>> + MachineBasicBlock::iterator J = (I == MBB.begin() ? I : prior
>> (I));
>> + while (J != MBB.begin()) {
>> + if (J->modifiesRegister(SrcReg, TRI))
>> + break;
>> + --J;
>> + }
>> +
>> + unsigned Domain;
>> + if (J->modifiesRegister(SrcReg, TRI)) {
>> + Domain = J->getDesc().TSFlags & ARMII::DomainMask;
>> + // Instructions in general domain are subreg accesses.
>> + // Map them to NEON reg-reg moves.
>> + if (Domain == ARMII::DomainGeneral)
>> + Domain = ARMII::DomainNEON;
>> + } else {
>> + // We reached the beginning of the BB and found no
>> instruction defining
>> + // the reg. This means that register should be live-in for
>> this BB.
>> + // It's always to better to use NEON reg-reg moves.
>> + Domain = ARMII::DomainNEON;
>> + }
>> +
>> + if ((Domain & ARMII::DomainNEON) && getSubtarget().hasNEON()) {
>> + BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
>> + } else {
>> + assert((Domain & ARMII::DomainVFP ||
>> + !getSubtarget().hasNEON()) && "Invalid domain!");
>> + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
>> + .addReg(SrcReg));
>> + }
>> } else if (DestRC == ARM::QPRRegisterClass ||
>> DestRC == ARM::QPR_VFP2RegisterClass) {
>> BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=85764&r1=85763&r2=85764&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Sun Nov 1 18:10:38
>> 2009
>> @@ -131,6 +131,14 @@
>> Xform16Bit = 1 << 16,
>>
>> //
>> ===------------------------------------------------------------------
>> ===//
>> + // Code domain.
>> + DomainShift = 17,
>> + DomainMask = 3 << DomainShift,
>> + DomainGeneral = 0 << DomainShift,
>> + DomainVFP = 1 << DomainShift,
>> + DomainNEON = 2 << DomainShift,
>> +
>> + //
>> ===------------------------------------------------------------------
>> ===//
>> // Field shifts - such shifts are used to set field while
>> generating
>> // machine instructions.
>> M_BitShift = 5,
>> @@ -157,9 +165,10 @@
>> }
>>
>> class ARMBaseInstrInfo : public TargetInstrInfoImpl {
>> + const ARMSubtarget& Subtarget;
>> protected:
>> // Can be only subclassed.
>> - explicit ARMBaseInstrInfo();
>> + explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
>> public:
>> // Return the non-pre/post incrementing version of 'Opc'. Return 0
>> // if there is not such an opcode.
>> @@ -173,6 +182,7 @@
>> LiveVariables *LV)
>> const;
>>
>> virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
>> + const ARMSubtarget &getSubtarget() const { return Subtarget; }
>>
>> // Branch analysis.
>> virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
>> MachineBasicBlock *&TBB,
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=85764&r1=85763&r2=85764&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Sun Nov 1 18:10:38
>> 2009
>> @@ -108,6 +108,15 @@
>> def IndexModePre : IndexMode<1>;
>> def IndexModePost : IndexMode<2>;
>>
>> +// Instruction execution domain.
>> +class Domain<bits<2> val> {
>> + bits<2> Value = val;
>> +}
>> +def GenericDomain : Domain<0>;
>> +def VFPDomain : Domain<1>; // Instructions in VFP domain only
>> +def NeonDomain : Domain<2>; // Instructions in Neon domain only
>> +def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon
>> domains
>> +
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> // ARM special operands.
>> @@ -136,7 +145,7 @@
>> //
>>
>> class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
>> - Format f, string cstr, InstrItinClass itin>
>> + Format f, Domain d, string cstr, InstrItinClass itin>
>> : Instruction {
>> field bits<32> Inst;
>>
>> @@ -155,6 +164,9 @@
>> Format F = f;
>> bits<5> Form = F.Value;
>>
>> + Domain D = d;
>> + bits<2> Dom = D.Value;
>> +
>> //
>> // Attributes specific to ARM instructions...
>> //
>> @@ -167,7 +179,8 @@
>>
>> class PseudoInst<dag oops, dag iops, InstrItinClass itin,
>> string asm, list<dag> pattern>
>> - : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, "",
>> itin> {
>> + : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo,
>> GenericDomain,
>> + "", itin> {
>> let OutOperandList = oops;
>> let InOperandList = iops;
>> let AsmString = asm;
>> @@ -179,7 +192,7 @@
>> IndexMode im, Format f, InstrItinClass itin,
>> string opc, string asm, string cstr,
>> list<dag> pattern>
>> - : InstARM<am, sz, im, f, cstr, itin> {
>> + : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
>> let OutOperandList = oops;
>> let InOperandList = !con(iops, (ops pred:$p));
>> let AsmString = !strconcat(opc, !strconcat("${p}", asm));
>> @@ -194,7 +207,7 @@
>> IndexMode im, Format f, InstrItinClass itin,
>> string opc, string asm, string cstr,
>> list<dag> pattern>
>> - : InstARM<am, sz, im, f, cstr, itin> {
>> + : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
>> let OutOperandList = oops;
>> let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
>> let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
>> @@ -206,7 +219,7 @@
>> class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
>> IndexMode im, Format f, InstrItinClass itin,
>> string asm, string cstr, list<dag> pattern>
>> - : InstARM<am, sz, im, f, cstr, itin> {
>> + : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
>> let OutOperandList = oops;
>> let InOperandList = iops;
>> let AsmString = asm;
>> @@ -807,7 +820,7 @@
>>
>> class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
>> InstrItinClass itin, string asm, string cstr, list<dag>
>> pattern>
>> - : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr, itin> {
>> + : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr,
>> itin> {
>> let OutOperandList = oops;
>> let InOperandList = iops;
>> let AsmString = asm;
>> @@ -833,7 +846,7 @@
>> // Thumb1 only
>> class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
>> InstrItinClass itin, string asm, string cstr,
>> list<dag> pattern>
>> - : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr, itin> {
>> + : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr,
>> itin> {
>> let OutOperandList = oops;
>> let InOperandList = iops;
>> let AsmString = asm;
>> @@ -861,7 +874,7 @@
>> class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
>> InstrItinClass itin,
>> string opc, string asm, string cstr, list<dag> pattern>
>> - : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr, itin> {
>> + : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr,
>> itin> {
>> let OutOperandList = !con(oops, (ops s_cc_out:$s));
>> let InOperandList = !con(iops, (ops pred:$p));
>> let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
>> @@ -883,7 +896,7 @@
>> class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
>> InstrItinClass itin,
>> string opc, string asm, string cstr, list<dag> pattern>
>> - : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr, itin> {
>> + : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr,
>> itin> {
>> let OutOperandList = oops;
>> let InOperandList = !con(iops, (ops pred:$p));
>> let AsmString = !strconcat(opc, !strconcat("${p}", asm));
>> @@ -918,7 +931,7 @@
>> class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
>> InstrItinClass itin,
>> string opc, string asm, string cstr, list<dag> pattern>
>> - : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr, itin> {
>> + : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr,
>> itin> {
>> let OutOperandList = oops;
>> let InOperandList = !con(iops, (ops pred:$p));
>> let AsmString = !strconcat(opc, !strconcat("${p}", asm));
>> @@ -934,7 +947,7 @@
>> class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
>> InstrItinClass itin,
>> string opc, string asm, string cstr, list<dag> pattern>
>> - : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr, itin> {
>> + : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr,
>> itin> {
>> let OutOperandList = oops;
>> let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
>> let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
>> @@ -946,7 +959,7 @@
>> class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
>> InstrItinClass itin,
>> string asm, string cstr, list<dag> pattern>
>> - : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr, itin> {
>> + : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr,
>> itin> {
>> let OutOperandList = oops;
>> let InOperandList = iops;
>> let AsmString = asm;
>> @@ -993,7 +1006,7 @@
>> class T2Iidxldst<dag oops, dag iops, AddrMode am, IndexMode im,
>> InstrItinClass itin,
>> string opc, string asm, string cstr, list<dag>
>> pattern>
>> - : InstARM<am, Size4Bytes, im, ThumbFrm, cstr, itin> {
>> + : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr,
>> itin> {
>> let OutOperandList = oops;
>> let InOperandList = !con(iops, (ops pred:$p));
>> let AsmString = !strconcat(opc, !strconcat("${p}", asm));
>> @@ -1026,7 +1039,7 @@
>> class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
>> IndexMode im, Format f, InstrItinClass itin,
>> string opc, string asm, string cstr, list<dag> pattern>
>> - : InstARM<am, sz, im, f, cstr, itin> {
>> + : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
>> let OutOperandList = oops;
>> let InOperandList = !con(iops, (ops pred:$p));
>> let AsmString = !strconcat(opc, !strconcat("${p}", asm));
>> @@ -1038,7 +1051,7 @@
>> class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
>> IndexMode im, Format f, InstrItinClass itin,
>> string asm, string cstr, list<dag> pattern>
>> - : InstARM<am, sz, im, f, cstr, itin> {
>> + : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
>> let OutOperandList = oops;
>> let InOperandList = iops;
>> let AsmString = asm;
>> @@ -1199,7 +1212,7 @@
>>
>> class NeonI<dag oops, dag iops, AddrMode am, IndexMode im,
>> InstrItinClass itin,
>> string asm, string cstr, list<dag> pattern>
>> - : InstARM<am, Size4Bytes, im, NEONFrm, cstr, itin> {
>> + : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
>> let OutOperandList = oops;
>> let InOperandList = iops;
>> let AsmString = asm;
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=85764&r1=85763&r2=85764&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Sun Nov 1 18:10:38
>> 2009
>> @@ -25,7 +25,7 @@
>> using namespace llvm;
>>
>> ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
>> - : RI(*this, STI), Subtarget(STI) {
>> + : ARMBaseInstrInfo(STI), RI(*this, STI) {
>> }
>>
>> unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=85764&r1=85763&r2=85764&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Sun Nov 1 18:10:38 2009
>> @@ -25,7 +25,6 @@
>>
>> class ARMInstrInfo : public ARMBaseInstrInfo {
>> ARMRegisterInfo RI;
>> - const ARMSubtarget &Subtarget;
>> public:
>> explicit ARMInstrInfo(const ARMSubtarget &STI);
>>
>>
>> Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=85764&r1=85763&r2=85764&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Sun Nov 1
>> 18:10:38 2009
>> @@ -24,7 +24,8 @@
>>
>> using namespace llvm;
>>
>> -Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) : RI
>> (*this, STI) {
>> +Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
>> + : ARMBaseInstrInfo(STI), RI(*this, STI) {
>> }
>>
>> unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
>>
>> Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=85764&r1=85763&r2=85764&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Sun Nov 1
>> 18:10:38 2009
>> @@ -25,7 +25,8 @@
>>
>> using namespace llvm;
>>
>> -Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI) : RI
>> (*this, STI) {
>> +Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
>> + : ARMBaseInstrInfo(STI), RI(*this, STI) {
>> }
>>
>> unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
>>
>>
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