[llvm-commits] [llvm] r85186 - /llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
Chris Lattner
clattner at apple.com
Mon Oct 26 17:42:14 PDT 2009
On Oct 26, 2009, at 5:20 PM, Evan Cheng wrote:
> Author: evancheng
> Date: Mon Oct 26 19:20:49 2009
> New Revision: 85186
>
> URL: http://llvm.org/viewvc/llvm-project?rev=85186&view=rev
> Log:
> Now VFP instructions.
Should the separator go in the ADI5 or higher level instcombine classes?
-Chris
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=85186&r1=85185&r2=85186&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Oct 26 19:20:49 2009
> @@ -36,20 +36,20 @@
>
> let canFoldAsLoad = 1 in {
> def FLDD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
> - IIC_fpLoad64, "fldd", " $dst, $addr",
> + IIC_fpLoad64, "fldd", "\t$dst, $addr",
> [(set DPR:$dst, (load addrmode5:$addr))]>;
>
> def FLDS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
> - IIC_fpLoad32, "flds", " $dst, $addr",
> + IIC_fpLoad32, "flds", "\t$dst, $addr",
> [(set SPR:$dst, (load addrmode5:$addr))]>;
> } // canFoldAsLoad
>
> def FSTD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src,
> addrmode5:$addr),
> - IIC_fpStore64, "fstd", " $src, $addr",
> + IIC_fpStore64, "fstd", "\t$src, $addr",
> [(store DPR:$src, addrmode5:$addr)]>;
>
> def FSTS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src,
> addrmode5:$addr),
> - IIC_fpStore32, "fsts", " $src, $addr",
> + IIC_fpStore32, "fsts", "\t$src, $addr",
> [(store SPR:$src, addrmode5:$addr)]>;
>
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> @@ -59,14 +59,14 @@
> let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
> def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
> variable_ops), IIC_fpLoadm,
> - "fldm${addr:submode}d${p} ${addr:base}, $wb",
> + "fldm${addr:submode}d${p}\t${addr:base}, $wb",
> []> {
> let Inst{20} = 1;
> }
>
> def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
> variable_ops), IIC_fpLoadm,
> - "fldm${addr:submode}s${p} ${addr:base}, $wb",
> + "fldm${addr:submode}s${p}\t${addr:base}, $wb",
> []> {
> let Inst{20} = 1;
> }
> @@ -75,14 +75,14 @@
> let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
> def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
> variable_ops), IIC_fpStorem,
> - "fstm${addr:submode}d${p} ${addr:base}, $wb",
> + "fstm${addr:submode}d${p}\t${addr:base}, $wb",
> []> {
> let Inst{20} = 0;
> }
>
> def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
> variable_ops), IIC_fpStorem,
> - "fstm${addr:submode}s${p} ${addr:base}, $wb",
> + "fstm${addr:submode}s${p}\t${addr:base}, $wb",
> []> {
> let Inst{20} = 0;
> }
> @@ -95,48 +95,48 @@
> //
>
> def FADDD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
> - IIC_fpALU64, "faddd", " $dst, $a, $b",
> + IIC_fpALU64, "faddd", "\t$dst, $a, $b",
> [(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
>
> def FADDS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
> - IIC_fpALU32, "fadds", " $dst, $a, $b",
> + IIC_fpALU32, "fadds", "\t$dst, $a, $b",
> [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
>
> // These are encoded as unary instructions.
> let Defs = [FPSCR] in {
> def FCMPED : ADuI<0b11101011, 0b0100, 0b1100, (outs), (ins DPR:$a,
> DPR:$b),
> - IIC_fpCMP64, "fcmped", " $a, $b",
> + IIC_fpCMP64, "fcmped", "\t$a, $b",
> [(arm_cmpfp DPR:$a, DPR:$b)]>;
>
> def FCMPES : ASuI<0b11101011, 0b0100, 0b1100, (outs), (ins SPR:$a,
> SPR:$b),
> - IIC_fpCMP32, "fcmpes", " $a, $b",
> + IIC_fpCMP32, "fcmpes", "\t$a, $b",
> [(arm_cmpfp SPR:$a, SPR:$b)]>;
> }
>
> def FDIVD : ADbI<0b11101000, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
> - IIC_fpDIV64, "fdivd", " $dst, $a, $b",
> + IIC_fpDIV64, "fdivd", "\t$dst, $a, $b",
> [(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
>
> def FDIVS : ASbI<0b11101000, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
> - IIC_fpDIV32, "fdivs", " $dst, $a, $b",
> + IIC_fpDIV32, "fdivs", "\t$dst, $a, $b",
> [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
>
> def FMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
> - IIC_fpMUL64, "fmuld", " $dst, $a, $b",
> + IIC_fpMUL64, "fmuld", "\t$dst, $a, $b",
> [(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
>
> def FMULS : ASbIn<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
> - IIC_fpMUL32, "fmuls", " $dst, $a, $b",
> + IIC_fpMUL32, "fmuls", "\t$dst, $a, $b",
> [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
>
> def FNMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
> - IIC_fpMUL64, "fnmuld", " $dst, $a, $b",
> + IIC_fpMUL64, "fnmuld", "\t$dst, $a, $b",
> [(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]> {
> let Inst{6} = 1;
> }
>
> def FNMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
> - IIC_fpMUL32, "fnmuls", " $dst, $a, $b",
> + IIC_fpMUL32, "fnmuls", "\t$dst, $a, $b",
> [(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]> {
> let Inst{6} = 1;
> }
> @@ -149,13 +149,13 @@
>
>
> def FSUBD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
> - IIC_fpALU64, "fsubd", " $dst, $a, $b",
> + IIC_fpALU64, "fsubd", "\t$dst, $a, $b",
> [(set DPR:$dst, (fsub DPR:$a, DPR:$b))]> {
> let Inst{6} = 1;
> }
>
> def FSUBS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
> - IIC_fpALU32, "fsubs", " $dst, $a, $b",
> + IIC_fpALU32, "fsubs", "\t$dst, $a, $b",
> [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]> {
> let Inst{6} = 1;
> }
> @@ -165,30 +165,30 @@
> //
>
> def FABSD : ADuI<0b11101011, 0b0000, 0b1100, (outs DPR:$dst), (ins
> DPR:$a),
> - IIC_fpUNA64, "fabsd", " $dst, $a",
> + IIC_fpUNA64, "fabsd", "\t$dst, $a",
> [(set DPR:$dst, (fabs DPR:$a))]>;
>
> def FABSS : ASuIn<0b11101011, 0b0000, 0b1100, (outs SPR:$dst), (ins
> SPR:$a),
> - IIC_fpUNA32, "fabss", " $dst, $a",
> + IIC_fpUNA32, "fabss", "\t$dst, $a",
> [(set SPR:$dst, (fabs SPR:$a))]>;
>
> let Defs = [FPSCR] in {
> def FCMPEZD : ADuI<0b11101011, 0b0101, 0b1100, (outs), (ins DPR:$a),
> - IIC_fpCMP64, "fcmpezd", " $a",
> + IIC_fpCMP64, "fcmpezd", "\t$a",
> [(arm_cmpfp0 DPR:$a)]>;
>
> def FCMPEZS : ASuI<0b11101011, 0b0101, 0b1100, (outs), (ins SPR:$a),
> - IIC_fpCMP32, "fcmpezs", " $a",
> + IIC_fpCMP32, "fcmpezs", "\t$a",
> [(arm_cmpfp0 SPR:$a)]>;
> }
>
> def FCVTDS : ASuI<0b11101011, 0b0111, 0b1100, (outs DPR:$dst), (ins
> SPR:$a),
> - IIC_fpCVTDS, "fcvtds", " $dst, $a",
> + IIC_fpCVTDS, "fcvtds", "\t$dst, $a",
> [(set DPR:$dst, (fextend SPR:$a))]>;
>
> // Special case encoding: bits 11-8 is 0b1011.
> def FCVTSD : VFPAI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
> - IIC_fpCVTSD, "fcvtsd", " $dst, $a",
> + IIC_fpCVTSD, "fcvtsd", "\t$dst, $a",
> [(set SPR:$dst, (fround DPR:$a))]> {
> let Inst{27-23} = 0b11101;
> let Inst{21-16} = 0b110111;
> @@ -198,26 +198,26 @@
>
> let neverHasSideEffects = 1 in {
> def FCPYD : ADuI<0b11101011, 0b0000, 0b0100, (outs DPR:$dst), (ins
> DPR:$a),
> - IIC_fpUNA64, "fcpyd", " $dst, $a", []>;
> + IIC_fpUNA64, "fcpyd", "\t$dst, $a", []>;
>
> def FCPYS : ASuI<0b11101011, 0b0000, 0b0100, (outs SPR:$dst), (ins
> SPR:$a),
> - IIC_fpUNA32, "fcpys", " $dst, $a", []>;
> + IIC_fpUNA32, "fcpys", "\t$dst, $a", []>;
> } // neverHasSideEffects
>
> def FNEGD : ADuI<0b11101011, 0b0001, 0b0100, (outs DPR:$dst), (ins
> DPR:$a),
> - IIC_fpUNA64, "fnegd", " $dst, $a",
> + IIC_fpUNA64, "fnegd", "\t$dst, $a",
> [(set DPR:$dst, (fneg DPR:$a))]>;
>
> def FNEGS : ASuIn<0b11101011, 0b0001, 0b0100, (outs SPR:$dst), (ins
> SPR:$a),
> - IIC_fpUNA32, "fnegs", " $dst, $a",
> + IIC_fpUNA32, "fnegs", "\t$dst, $a",
> [(set SPR:$dst, (fneg SPR:$a))]>;
>
> def FSQRTD : ADuI<0b11101011, 0b0001, 0b1100, (outs DPR:$dst), (ins
> DPR:$a),
> - IIC_fpSQRT64, "fsqrtd", " $dst, $a",
> + IIC_fpSQRT64, "fsqrtd", "\t$dst, $a",
> [(set DPR:$dst, (fsqrt DPR:$a))]>;
>
> def FSQRTS : ASuI<0b11101011, 0b0001, 0b1100, (outs SPR:$dst), (ins
> SPR:$a),
> - IIC_fpSQRT32, "fsqrts", " $dst, $a",
> + IIC_fpSQRT32, "fsqrts", "\t$dst, $a",
> [(set SPR:$dst, (fsqrt SPR:$a))]>;
>
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> @@ -225,16 +225,16 @@
> //
>
> def FMRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:
> $src),
> - IIC_VMOVSI, "fmrs", " $dst, $src",
> + IIC_VMOVSI, "fmrs", "\t$dst, $src",
> [(set GPR:$dst, (bitconvert SPR:$src))]>;
>
> def FMSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:
> $src),
> - IIC_VMOVIS, "fmsr", " $dst, $src",
> + IIC_VMOVIS, "fmsr", "\t$dst, $src",
> [(set SPR:$dst, (bitconvert GPR:$src))]>;
>
> def FMRRD : AVConv3I<0b11000101, 0b1011,
> (outs GPR:$wb, GPR:$dst2), (ins DPR:$src),
> - IIC_VMOVDI, "fmrrd", " $wb, $dst2, $src",
> + IIC_VMOVDI, "fmrrd", "\t$wb, $dst2, $src",
> [/* FIXME: Can't write pattern for multiple result
> instr*/]>;
>
> // FMDHR: GPR -> SPR
> @@ -242,7 +242,7 @@
>
> def FMDRR : AVConv5I<0b11000100, 0b1011,
> (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
> - IIC_VMOVID, "fmdrr", " $dst, $src1, $src2",
> + IIC_VMOVID, "fmdrr", "\t$dst, $src1, $src2",
> [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
>
> // FMRDH: SPR -> GPR
> @@ -258,23 +258,23 @@
> // Int to FP:
>
> def FSITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst),
> (ins SPR:$a),
> - IIC_fpCVTID, "fsitod", " $dst, $a",
> + IIC_fpCVTID, "fsitod", "\t$dst, $a",
> [(set DPR:$dst, (arm_sitof SPR:$a))]> {
> let Inst{7} = 1;
> }
>
> def FSITOS : AVConv1In<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),
> (ins SPR:$a),
> - IIC_fpCVTIS, "fsitos", " $dst, $a",
> + IIC_fpCVTIS, "fsitos", "\t$dst, $a",
> [(set SPR:$dst, (arm_sitof SPR:$a))]> {
> let Inst{7} = 1;
> }
>
> def FUITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst),
> (ins SPR:$a),
> - IIC_fpCVTID, "fuitod", " $dst, $a",
> + IIC_fpCVTID, "fuitod", "\t$dst, $a",
> [(set DPR:$dst, (arm_uitof SPR:$a))]>;
>
> def FUITOS : AVConv1In<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),
> (ins SPR:$a),
> - IIC_fpCVTIS, "fuitos", " $dst, $a",
> + IIC_fpCVTIS, "fuitos", "\t$dst, $a",
> [(set SPR:$dst, (arm_uitof SPR:$a))]>;
>
> // FP to Int:
> @@ -282,28 +282,28 @@
>
> def FTOSIZD : AVConv1I<0b11101011, 0b1101, 0b1011,
> (outs SPR:$dst), (ins DPR:$a),
> - IIC_fpCVTDI, "ftosizd", " $dst, $a",
> + IIC_fpCVTDI, "ftosizd", "\t$dst, $a",
> [(set SPR:$dst, (arm_ftosi DPR:$a))]> {
> let Inst{7} = 1; // Z bit
> }
>
> def FTOSIZS : AVConv1In<0b11101011, 0b1101, 0b1010,
> (outs SPR:$dst), (ins SPR:$a),
> - IIC_fpCVTSI, "ftosizs", " $dst, $a",
> + IIC_fpCVTSI, "ftosizs", "\t$dst, $a",
> [(set SPR:$dst, (arm_ftosi SPR:$a))]> {
> let Inst{7} = 1; // Z bit
> }
>
> def FTOUIZD : AVConv1I<0b11101011, 0b1100, 0b1011,
> (outs SPR:$dst), (ins DPR:$a),
> - IIC_fpCVTDI, "ftouizd", " $dst, $a",
> + IIC_fpCVTDI, "ftouizd", "\t$dst, $a",
> [(set SPR:$dst, (arm_ftoui DPR:$a))]> {
> let Inst{7} = 1; // Z bit
> }
>
> def FTOUIZS : AVConv1In<0b11101011, 0b1100, 0b1010,
> (outs SPR:$dst), (ins SPR:$a),
> - IIC_fpCVTSI, "ftouizs", " $dst, $a",
> + IIC_fpCVTSI, "ftouizs", "\t$dst, $a",
> [(set SPR:$dst, (arm_ftoui SPR:$a))]> {
> let Inst{7} = 1; // Z bit
> }
> @@ -313,34 +313,34 @@
> //
>
> def FMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:
> $a, DPR:$b),
> - IIC_fpMAC64, "fmacd", " $dst, $a, $b",
> + IIC_fpMAC64, "fmacd", "\t$dst, $a, $b",
> [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:
> $dstin))]>,
> RegConstraint<"$dstin = $dst">;
>
> def FMACS : ASbIn<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:
> $a, SPR:$b),
> - IIC_fpMAC32, "fmacs", " $dst, $a, $b",
> + IIC_fpMAC32, "fmacs", "\t$dst, $a, $b",
> [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:
> $dstin))]>,
> RegConstraint<"$dstin = $dst">;
>
> def FMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:
> $a, DPR:$b),
> - IIC_fpMAC64, "fmscd", " $dst, $a, $b",
> + IIC_fpMAC64, "fmscd", "\t$dst, $a, $b",
> [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:
> $dstin))]>,
> RegConstraint<"$dstin = $dst">;
>
> def FMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:
> $a, SPR:$b),
> - IIC_fpMAC32, "fmscs", " $dst, $a, $b",
> + IIC_fpMAC32, "fmscs", "\t$dst, $a, $b",
> [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:
> $dstin))]>,
> RegConstraint<"$dstin = $dst">;
>
> def FNMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:
> $a, DPR:$b),
> - IIC_fpMAC64, "fnmacd", " $dst, $a, $b",
> + IIC_fpMAC64, "fnmacd", "\t$dst, $a, $b",
> [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:
> $dstin))]>,
> RegConstraint<"$dstin = $dst"> {
> let Inst{6} = 1;
> }
>
> def FNMACS : ASbIn<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:
> $a, SPR:$b),
> - IIC_fpMAC32, "fnmacs", " $dst, $a, $b",
> + IIC_fpMAC32, "fnmacs", "\t$dst, $a, $b",
> [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:
> $dstin))]>,
> RegConstraint<"$dstin = $dst"> {
> let Inst{6} = 1;
> @@ -352,14 +352,14 @@
> (FNMACS SPR:$dstin, SPR:$a, SPR:$b)>,
> Requires<[DontUseNEONForFP]>;
>
> def FNMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:
> $a, DPR:$b),
> - IIC_fpMAC64, "fnmscd", " $dst, $a, $b",
> + IIC_fpMAC64, "fnmscd", "\t$dst, $a, $b",
> [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:
> $dstin))]>,
> RegConstraint<"$dstin = $dst"> {
> let Inst{6} = 1;
> }
>
> def FNMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:
> $a, SPR:$b),
> - IIC_fpMAC32, "fnmscs", " $dst, $a, $b",
> + IIC_fpMAC32, "fnmscs", "\t$dst, $a, $b",
> [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:
> $dstin))]>,
> RegConstraint<"$dstin = $dst"> {
> let Inst{6} = 1;
> @@ -371,25 +371,25 @@
>
> def FCPYDcc : ADuI<0b11101011, 0b0000, 0b0100,
> (outs DPR:$dst), (ins DPR:$false, DPR:$true),
> - IIC_fpUNA64, "fcpyd", " $dst, $true",
> + IIC_fpUNA64, "fcpyd", "\t$dst, $true",
> [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true,
> imm:$cc))*/]>,
> RegConstraint<"$false = $dst">;
>
> def FCPYScc : ASuI<0b11101011, 0b0000, 0b0100,
> (outs SPR:$dst), (ins SPR:$false, SPR:$true),
> - IIC_fpUNA32, "fcpys", " $dst, $true",
> + IIC_fpUNA32, "fcpys", "\t$dst, $true",
> [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true,
> imm:$cc))*/]>,
> RegConstraint<"$false = $dst">;
>
> def FNEGDcc : ADuI<0b11101011, 0b0001, 0b0100,
> (outs DPR:$dst), (ins DPR:$false, DPR:$true),
> - IIC_fpUNA64, "fnegd", " $dst, $true",
> + IIC_fpUNA64, "fnegd", "\t$dst, $true",
> [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true,
> imm:$cc))*/]>,
> RegConstraint<"$false = $dst">;
>
> def FNEGScc : ASuI<0b11101011, 0b0001, 0b0100,
> (outs SPR:$dst), (ins SPR:$false, SPR:$true),
> - IIC_fpUNA32, "fnegs", " $dst, $true",
> + IIC_fpUNA32, "fnegs", "\t$dst, $true",
> [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true,
> imm:$cc))*/]>,
> RegConstraint<"$false = $dst">;
>
> @@ -399,7 +399,8 @@
> //
>
> let Defs = [CPSR], Uses = [FPSCR] in
> -def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "fmstat",
> "", [(arm_fmstat)]> {
> +def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "fmstat",
> "",
> + [(arm_fmstat)]> {
> let Inst{27-20} = 0b11101111;
> let Inst{19-16} = 0b0001;
> let Inst{15-12} = 0b1111;
>
>
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