[llvm-commits] [llvm] r85184 - in /llvm/trunk/lib/Target/ARM: ARMInstrThumb.td ARMInstrThumb2.td
Evan Cheng
evan.cheng at apple.com
Mon Oct 26 17:08:59 PDT 2009
Author: evancheng
Date: Mon Oct 26 19:08:59 2009
New Revision: 85184
URL: http://llvm.org/viewvc/llvm-project?rev=85184&view=rev
Log:
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=85184&r1=85183&r2=85184&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Oct 26 19:08:59 2009
@@ -130,44 +130,44 @@
// For both thumb1 and thumb2.
let isNotDuplicable = 1 in
def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
- "\n$cp:\n\tadd $dst, pc",
+ "\n$cp:\n\tadd\t$dst, pc",
[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
// PC relative add.
def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), IIC_iALUi,
- "add $dst, pc, $rhs * 4", []>;
+ "add\t$dst, pc, $rhs * 4", []>;
// ADD rd, sp, #imm8
def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), IIC_iALUi,
- "add $dst, $sp, $rhs * 4", []>;
+ "add\t$dst, $sp, $rhs * 4", []>;
// ADD sp, sp, #imm7
def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi,
- "add $dst, $rhs * 4", []>;
+ "add\t$dst, $rhs * 4", []>;
// SUB sp, sp, #imm7
def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi,
- "sub $dst, $rhs * 4", []>;
+ "sub\t$dst, $rhs * 4", []>;
// ADD rm, sp
def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
- "add $dst, $rhs", []>;
+ "add\t$dst, $rhs", []>;
// ADD sp, rm
def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
- "add $dst, $rhs", []>;
+ "add\t$dst, $rhs", []>;
// Pseudo instruction that will expand into a tSUBspi + a copy.
let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
- NoItinerary, "@ sub $dst, $rhs * 4", []>;
+ NoItinerary, "@ sub\t$dst, $rhs * 4", []>;
def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
- NoItinerary, "@ add $dst, $rhs", []>;
+ NoItinerary, "@ add\t$dst, $rhs", []>;
let Defs = [CPSR] in
def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
- NoItinerary, "@ and $dst, $rhs", []>;
+ NoItinerary, "@ and\t$dst, $rhs", []>;
} // usesCustomDAGSchedInserter
//===----------------------------------------------------------------------===//
@@ -175,16 +175,16 @@
//
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
- def tBX_RET : TI<(outs), (ins), IIC_Br, "bx lr", [(ARMretflag)]>;
+ def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>;
// Alternative return instruction used by vararg functions.
- def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx $target", []>;
+ def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>;
}
// FIXME: remove when we have a way to marking a MI with these properties.
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1 in
def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
- "pop${p} $wb", []>;
+ "pop${p}\t$wb", []>;
let isCall = 1,
Defs = [R0, R1, R2, R3, R12, LR,
@@ -193,25 +193,25 @@
D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
// Also used for Thumb2
def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
- "bl ${func:call}",
+ "bl\t${func:call}",
[(ARMtcall tglobaladdr:$func)]>,
Requires<[IsThumb, IsNotDarwin]>;
// ARMv5T and above, also used for Thumb2
def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
- "blx ${func:call}",
+ "blx\t${func:call}",
[(ARMcall tglobaladdr:$func)]>,
Requires<[IsThumb, HasV5T, IsNotDarwin]>;
// Also used for Thumb2
def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
- "blx $func",
+ "blx\t$func",
[(ARMtcall GPR:$func)]>,
Requires<[IsThumb, HasV5T, IsNotDarwin]>;
// ARMv4T
def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
- "mov lr, pc\n\tbx $func",
+ "mov\tlr, pc\n\tbx\t$func",
[(ARMcall_nolink tGPR:$func)]>,
Requires<[IsThumb1Only, IsNotDarwin]>;
}
@@ -224,25 +224,25 @@
D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
// Also used for Thumb2
def tBLr9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
- "bl ${func:call}",
+ "bl\t${func:call}",
[(ARMtcall tglobaladdr:$func)]>,
Requires<[IsThumb, IsDarwin]>;
// ARMv5T and above, also used for Thumb2
def tBLXi_r9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
- "blx ${func:call}",
+ "blx\t${func:call}",
[(ARMcall tglobaladdr:$func)]>,
Requires<[IsThumb, HasV5T, IsDarwin]>;
// Also used for Thumb2
def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
- "blx $func",
+ "blx\t$func",
[(ARMtcall GPR:$func)]>,
Requires<[IsThumb, HasV5T, IsDarwin]>;
// ARMv4T
def tBXr9 : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
- "mov lr, pc\n\tbx $func",
+ "mov\tlr, pc\n\tbx\t$func",
[(ARMcall_nolink tGPR:$func)]>,
Requires<[IsThumb1Only, IsDarwin]>;
}
@@ -251,16 +251,16 @@
let isBarrier = 1 in {
let isPredicable = 1 in
def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
- "b $target", [(br bb:$target)]>;
+ "b\t$target", [(br bb:$target)]>;
// Far jump
let Defs = [LR] in
def tBfar : TIx2<(outs), (ins brtarget:$target), IIC_Br,
- "bl $target\t@ far jump",[]>;
+ "bl\t$target\t@ far jump",[]>;
def tBR_JTr : T1JTI<(outs),
(ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
- IIC_Br, "mov pc, $target\n\t.align\t2\n$jt",
+ IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt",
[(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
}
}
@@ -269,7 +269,7 @@
// a two-value operand where a dag node expects two operands. :(
let isBranch = 1, isTerminator = 1 in
def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
- "b$cc $target",
+ "b$cc\t$target",
[/*(ARMbrcond bb:$target, imm:$cc)*/]>;
//===----------------------------------------------------------------------===//
@@ -278,70 +278,70 @@
let canFoldAsLoad = 1 in
def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
- "ldr", " $dst, $addr",
+ "ldr", "\t$dst, $addr",
[(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
- "ldrb", " $dst, $addr",
+ "ldrb", "\t$dst, $addr",
[(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
- "ldrh", " $dst, $addr",
+ "ldrh", "\t$dst, $addr",
[(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
let AddedComplexity = 10 in
def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
- "ldrsb", " $dst, $addr",
+ "ldrsb", "\t$dst, $addr",
[(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
let AddedComplexity = 10 in
def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
- "ldrsh", " $dst, $addr",
+ "ldrsh", "\t$dst, $addr",
[(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
let canFoldAsLoad = 1 in
def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
- "ldr", " $dst, $addr",
+ "ldr", "\t$dst, $addr",
[(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
// Special instruction for restore. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr().
let canFoldAsLoad = 1, mayLoad = 1 in
def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
- "ldr", " $dst, $addr", []>;
+ "ldr", "\t$dst, $addr", []>;
// Load tconstpool
let canFoldAsLoad = 1 in
def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
- "ldr", " $dst, $addr",
+ "ldr", "\t$dst, $addr",
[(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
// Special LDR for loads from non-pc-relative constpools.
let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
- "ldr", " $dst, $addr", []>;
+ "ldr", "\t$dst, $addr", []>;
def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
- "str", " $src, $addr",
+ "str", "\t$src, $addr",
[(store tGPR:$src, t_addrmode_s4:$addr)]>;
def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
- "strb", " $src, $addr",
+ "strb", "\t$src, $addr",
[(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
- "strh", " $src, $addr",
+ "strh", "\t$src, $addr",
[(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
- "str", " $src, $addr",
+ "str", "\t$src, $addr",
[(store tGPR:$src, t_addrmode_sp:$addr)]>;
let mayStore = 1 in {
// Special instruction for spill. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr().
def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
- "str", " $src, $addr", []>;
+ "str", "\t$src, $addr", []>;
}
//===----------------------------------------------------------------------===//
@@ -353,21 +353,21 @@
def tLDM : T1I<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
IIC_iLoadm,
- "ldm${addr:submode}${p} $addr, $wb", []>;
+ "ldm${addr:submode}${p}\t$addr, $wb", []>;
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
def tSTM : T1I<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
IIC_iStorem,
- "stm${addr:submode}${p} $addr, $wb", []>;
+ "stm${addr:submode}${p}\t$addr, $wb", []>;
let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
- "pop${p} $wb", []>;
+ "pop${p}\t$wb", []>;
let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
- "push${p} $wb", []>;
+ "push${p}\t$wb", []>;
//===----------------------------------------------------------------------===//
// Arithmetic Instructions.
@@ -376,66 +376,66 @@
// Add with carry register
let isCommutable = 1, Uses = [CPSR] in
def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
- "adc", " $dst, $rhs",
+ "adc", "\t$dst, $rhs",
[(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
// Add immediate
def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
- "add", " $dst, $lhs, $rhs",
+ "add", "\t$dst, $lhs, $rhs",
[(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
- "add", " $dst, $rhs",
+ "add", "\t$dst, $rhs",
[(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
// Add register
let isCommutable = 1 in
def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
- "add", " $dst, $lhs, $rhs",
+ "add", "\t$dst, $lhs, $rhs",
[(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
let neverHasSideEffects = 1 in
def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
- "add", " $dst, $rhs", []>;
+ "add", "\t$dst, $rhs", []>;
// And register
let isCommutable = 1 in
def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
- "and", " $dst, $rhs",
+ "and", "\t$dst, $rhs",
[(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
// ASR immediate
def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
- "asr", " $dst, $lhs, $rhs",
+ "asr", "\t$dst, $lhs, $rhs",
[(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
// ASR register
def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
- "asr", " $dst, $rhs",
+ "asr", "\t$dst, $rhs",
[(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
// BIC register
def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
- "bic", " $dst, $rhs",
+ "bic", "\t$dst, $rhs",
[(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
// CMN register
let Defs = [CPSR] in {
def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
- "cmn", " $lhs, $rhs",
+ "cmn", "\t$lhs, $rhs",
[(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
- "cmn", " $lhs, $rhs",
+ "cmn", "\t$lhs, $rhs",
[(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
}
// CMP immediate
let Defs = [CPSR] in {
def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
- "cmp", " $lhs, $rhs",
+ "cmp", "\t$lhs, $rhs",
[(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
- "cmp", " $lhs, $rhs",
+ "cmp", "\t$lhs, $rhs",
[(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
}
@@ -443,48 +443,48 @@
// CMP register
let Defs = [CPSR] in {
def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
- "cmp", " $lhs, $rhs",
+ "cmp", "\t$lhs, $rhs",
[(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
- "cmp", " $lhs, $rhs",
+ "cmp", "\t$lhs, $rhs",
[(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
- "cmp", " $lhs, $rhs", []>;
+ "cmp", "\t$lhs, $rhs", []>;
def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
- "cmp", " $lhs, $rhs", []>;
+ "cmp", "\t$lhs, $rhs", []>;
}
// XOR register
let isCommutable = 1 in
def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
- "eor", " $dst, $rhs",
+ "eor", "\t$dst, $rhs",
[(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
// LSL immediate
def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
- "lsl", " $dst, $lhs, $rhs",
+ "lsl", "\t$dst, $lhs, $rhs",
[(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
// LSL register
def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
- "lsl", " $dst, $rhs",
+ "lsl", "\t$dst, $rhs",
[(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
// LSR immediate
def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
- "lsr", " $dst, $lhs, $rhs",
+ "lsr", "\t$dst, $lhs, $rhs",
[(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
// LSR register
def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
- "lsr", " $dst, $rhs",
+ "lsr", "\t$dst, $rhs",
[(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
// move register
def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
- "mov", " $dst, $src",
+ "mov", "\t$dst, $src",
[(set tGPR:$dst, imm0_255:$src)]>;
// TODO: A7-73: MOV(2) - mov setting flag.
@@ -493,45 +493,45 @@
let neverHasSideEffects = 1 in {
// FIXME: Make this predicable.
def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
- "mov $dst, $src", []>;
+ "mov\t$dst, $src", []>;
let Defs = [CPSR] in
def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
- "movs $dst, $src", []>;
+ "movs\t$dst, $src", []>;
// FIXME: Make these predicable.
def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
- "mov $dst, $src", []>;
+ "mov\t$dst, $src", []>;
def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
- "mov $dst, $src", []>;
+ "mov\t$dst, $src", []>;
def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
- "mov $dst, $src", []>;
+ "mov\t$dst, $src", []>;
} // neverHasSideEffects
// multiply register
let isCommutable = 1 in
def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
- "mul", " $dst, $rhs",
+ "mul", "\t$dst, $rhs",
[(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
// move inverse register
def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
- "mvn", " $dst, $src",
+ "mvn", "\t$dst, $src",
[(set tGPR:$dst, (not tGPR:$src))]>;
// bitwise or register
let isCommutable = 1 in
def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
- "orr", " $dst, $rhs",
+ "orr", "\t$dst, $rhs",
[(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
// swaps
def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
- "rev", " $dst, $src",
+ "rev", "\t$dst, $src",
[(set tGPR:$dst, (bswap tGPR:$src))]>,
Requires<[IsThumb1Only, HasV6]>;
def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
- "rev16", " $dst, $src",
+ "rev16", "\t$dst, $src",
[(set tGPR:$dst,
(or (and (srl tGPR:$src, (i32 8)), 0xFF),
(or (and (shl tGPR:$src, (i32 8)), 0xFF00),
@@ -540,7 +540,7 @@
Requires<[IsThumb1Only, HasV6]>;
def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
- "revsh", " $dst, $src",
+ "revsh", "\t$dst, $src",
[(set tGPR:$dst,
(sext_inreg
(or (srl (and tGPR:$src, 0xFF00), (i32 8)),
@@ -549,63 +549,63 @@
// rotate right register
def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
- "ror", " $dst, $rhs",
+ "ror", "\t$dst, $rhs",
[(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
// negate register
def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
- "rsb", " $dst, $src, #0",
+ "rsb", "\t$dst, $src, #0",
[(set tGPR:$dst, (ineg tGPR:$src))]>;
// Subtract with carry register
let Uses = [CPSR] in
def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
- "sbc", " $dst, $rhs",
+ "sbc", "\t$dst, $rhs",
[(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
// Subtract immediate
def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
- "sub", " $dst, $lhs, $rhs",
+ "sub", "\t$dst, $lhs, $rhs",
[(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
- "sub", " $dst, $rhs",
+ "sub", "\t$dst, $rhs",
[(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
// subtract register
def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
- "sub", " $dst, $lhs, $rhs",
+ "sub", "\t$dst, $lhs, $rhs",
[(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
// TODO: A7-96: STMIA - store multiple.
// sign-extend byte
def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
- "sxtb", " $dst, $src",
+ "sxtb", "\t$dst, $src",
[(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
Requires<[IsThumb1Only, HasV6]>;
// sign-extend short
def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
- "sxth", " $dst, $src",
+ "sxth", "\t$dst, $src",
[(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
Requires<[IsThumb1Only, HasV6]>;
// test
let isCommutable = 1, Defs = [CPSR] in
def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
- "tst", " $lhs, $rhs",
+ "tst", "\t$lhs, $rhs",
[(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
// zero-extend byte
def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
- "uxtb", " $dst, $src",
+ "uxtb", "\t$dst, $src",
[(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
Requires<[IsThumb1Only, HasV6]>;
// zero-extend short
def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
- "uxth", " $dst, $src",
+ "uxth", "\t$dst, $src",
[(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
Requires<[IsThumb1Only, HasV6]>;
@@ -621,19 +621,19 @@
// 16-bit movcc in IT blocks for Thumb2.
def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
- "mov", " $dst, $rhs", []>;
+ "mov", "\t$dst, $rhs", []>;
def tMOVCCi : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
- "mov", " $dst, $rhs", []>;
+ "mov", "\t$dst, $rhs", []>;
// tLEApcrel - Load a pc-relative address into a register without offending the
// assembler.
def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
- "adr$p $dst, #$label", []>;
+ "adr$p\t$dst, #$label", []>;
def tLEApcrelJT : T1I<(outs tGPR:$dst),
(ins i32imm:$label, nohash_imm:$id, pred:$p),
- IIC_iALUi, "adr$p $dst, #${label}_${id}", []>;
+ IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>;
//===----------------------------------------------------------------------===//
// TLS Instructions
@@ -643,7 +643,7 @@
let isCall = 1,
Defs = [R0, LR] in {
def tTPsoft : TIx2<(outs), (ins), IIC_Br,
- "bl __aeabi_read_tp",
+ "bl\t__aeabi_read_tp",
[(set R0, ARMthread_pointer)]>;
}
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=85184&r1=85183&r2=85184&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Oct 26 19:08:59 2009
@@ -153,18 +153,18 @@
multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
// shifted imm
def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
- opc, " $dst, $src",
+ opc, "\t$dst, $src",
[(set GPR:$dst, (opnode t2_so_imm:$src))]> {
let isAsCheapAsAMove = Cheap;
let isReMaterializable = ReMat;
}
// register
def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
- opc, ".w $dst, $src",
+ opc, ".w\t$dst, $src",
[(set GPR:$dst, (opnode GPR:$src))]>;
// shifted register
def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
- opc, ".w $dst, $src",
+ opc, ".w\t$dst, $src",
[(set GPR:$dst, (opnode t2_so_reg:$src))]>;
}
@@ -175,17 +175,17 @@
bit Commutable = 0, string wide =""> {
// shifted imm
def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
- opc, " $dst, $lhs, $rhs",
+ opc, "\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
// register
def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
- opc, !strconcat(wide, " $dst, $lhs, $rhs"),
+ opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
let isCommutable = Commutable;
}
// shifted register
def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
- opc, !strconcat(wide, " $dst, $lhs, $rhs"),
+ opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
}
@@ -200,11 +200,11 @@
multiclass T2I_rbin_is<string opc, PatFrag opnode> {
// shifted imm
def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
- opc, ".w $dst, $rhs, $lhs",
+ opc, ".w\t$dst, $rhs, $lhs",
[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
// shifted register
def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
- opc, " $dst, $rhs, $lhs",
+ opc, "\t$dst, $rhs, $lhs",
[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
}
@@ -214,17 +214,17 @@
multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
// shifted imm
def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
- !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
+ !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
// register
def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
- !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
+ !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
let isCommutable = Commutable;
}
// shifted register
def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
- !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
+ !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
}
}
@@ -234,21 +234,21 @@
multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
// shifted imm
def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
- opc, ".w $dst, $lhs, $rhs",
+ opc, ".w\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
// 12-bit imm
def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
- !strconcat(opc, "w"), " $dst, $lhs, $rhs",
+ !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
// register
def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
- opc, ".w $dst, $lhs, $rhs",
+ opc, ".w\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
let isCommutable = Commutable;
}
// shifted register
def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
- opc, ".w $dst, $lhs, $rhs",
+ opc, ".w\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
}
@@ -259,32 +259,32 @@
multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
// shifted imm
def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
- opc, " $dst, $lhs, $rhs",
+ opc, "\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
Requires<[IsThumb2, CarryDefIsUnused]>;
// register
def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
- opc, ".w $dst, $lhs, $rhs",
+ opc, ".w\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
Requires<[IsThumb2, CarryDefIsUnused]> {
let isCommutable = Commutable;
}
// shifted register
def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
- opc, ".w $dst, $lhs, $rhs",
+ opc, ".w\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
Requires<[IsThumb2, CarryDefIsUnused]>;
// Carry setting variants
// shifted imm
def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
- !strconcat(opc, "s $dst, $lhs, $rhs"),
+ !strconcat(opc, "s\t$dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
Requires<[IsThumb2, CarryDefIsUsed]> {
let Defs = [CPSR];
}
// register
def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
- !strconcat(opc, "s.w $dst, $lhs, $rhs"),
+ !strconcat(opc, "s.w\t$dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
Requires<[IsThumb2, CarryDefIsUsed]> {
let Defs = [CPSR];
@@ -292,7 +292,7 @@
}
// shifted register
def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
- !strconcat(opc, "s.w $dst, $lhs, $rhs"),
+ !strconcat(opc, "s.w\t$dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
Requires<[IsThumb2, CarryDefIsUsed]> {
let Defs = [CPSR];
@@ -306,12 +306,12 @@
// shifted imm
def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
IIC_iALUi,
- !strconcat(opc, "${s}.w $dst, $rhs, $lhs"),
+ !strconcat(opc, "${s}.w\t$dst, $rhs, $lhs"),
[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
// shifted register
def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
IIC_iALUsi,
- !strconcat(opc, "${s} $dst, $rhs, $lhs"),
+ !strconcat(opc, "${s}\t$dst, $rhs, $lhs"),
[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
}
}
@@ -321,11 +321,11 @@
multiclass T2I_sh_ir<string opc, PatFrag opnode> {
// 5-bit imm
def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
- opc, ".w $dst, $lhs, $rhs",
+ opc, ".w\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
// register
def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
- opc, ".w $dst, $lhs, $rhs",
+ opc, ".w\t$dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
}
@@ -336,15 +336,15 @@
multiclass T2I_cmp_is<string opc, PatFrag opnode> {
// shifted imm
def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
- opc, ".w $lhs, $rhs",
+ opc, ".w\t$lhs, $rhs",
[(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
// register
def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
- opc, ".w $lhs, $rhs",
+ opc, ".w\t$lhs, $rhs",
[(opnode GPR:$lhs, GPR:$rhs)]>;
// shifted register
def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
- opc, ".w $lhs, $rhs",
+ opc, ".w\t$lhs, $rhs",
[(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
}
}
@@ -352,42 +352,42 @@
/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
multiclass T2I_ld<string opc, PatFrag opnode> {
def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
- opc, ".w $dst, $addr",
+ opc, ".w\t$dst, $addr",
[(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
- opc, " $dst, $addr",
+ opc, "\t$dst, $addr",
[(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
- opc, ".w $dst, $addr",
+ opc, ".w\t$dst, $addr",
[(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
- opc, ".w $dst, $addr",
+ opc, ".w\t$dst, $addr",
[(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
}
/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
multiclass T2I_st<string opc, PatFrag opnode> {
def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
- opc, ".w $src, $addr",
+ opc, ".w\t$src, $addr",
[(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
- opc, " $src, $addr",
+ opc, "\t$src, $addr",
[(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
- opc, ".w $src, $addr",
+ opc, ".w\t$src, $addr",
[(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
}
/// T2I_picld - Defines the PIC load pattern.
class T2I_picld<string opc, PatFrag opnode> :
T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoadi,
- !strconcat("\n${addr:label}:\n\t", opc), " $dst, $addr",
+ !strconcat("\n${addr:label}:\n\t", opc), "\t$dst, $addr",
[(set GPR:$dst, (opnode addrmodepc:$addr))]>;
/// T2I_picst - Defines the PIC store pattern.
class T2I_picst<string opc, PatFrag opnode> :
T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStorer,
- !strconcat("\n${addr:label}:\n\t", opc), " $src, $addr",
+ !strconcat("\n${addr:label}:\n\t", opc), "\t$src, $addr",
[(opnode GPR:$src, addrmodepc:$addr)]>;
@@ -395,10 +395,10 @@
/// register and one whose operand is a register rotated by 8/16/24.
multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
- opc, ".w $dst, $src",
+ opc, ".w\t$dst, $src",
[(set GPR:$dst, (opnode GPR:$src))]>;
def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
- opc, ".w $dst, $src, ror $rot",
+ opc, ".w\t$dst, $src, ror $rot",
[(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>;
}
@@ -406,10 +406,10 @@
/// register and one whose operand is a register rotated by 8/16/24.
multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
- opc, " $dst, $LHS, $RHS",
+ opc, "\t$dst, $LHS, $RHS",
[(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
- IIC_iALUsr, opc, " $dst, $LHS, $RHS, ror $rot",
+ IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
[(set GPR:$dst, (opnode GPR:$LHS,
(rotr GPR:$RHS, rot_imm:$rot)))]>;
}
@@ -425,42 +425,42 @@
// LEApcrel - Load a pc-relative address into a register without offending the
// assembler.
def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
- "adr$p.w $dst, #$label", []>;
+ "adr$p.w\t$dst, #$label", []>;
def t2LEApcrelJT : T2XI<(outs GPR:$dst),
(ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
- "adr$p.w $dst, #${label}_${id}", []>;
+ "adr$p.w\t$dst, #${label}_${id}", []>;
// ADD r, sp, {so_imm|i12}
def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
- IIC_iALUi, "add", ".w $dst, $sp, $imm", []>;
+ IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []>;
def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
- IIC_iALUi, "addw", " $dst, $sp, $imm", []>;
+ IIC_iALUi, "addw", "\t$dst, $sp, $imm", []>;
// ADD r, sp, so_reg
def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
- IIC_iALUsi, "add", ".w $dst, $sp, $rhs", []>;
+ IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []>;
// SUB r, sp, {so_imm|i12}
def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
- IIC_iALUi, "sub", ".w $dst, $sp, $imm", []>;
+ IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []>;
def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
- IIC_iALUi, "subw", " $dst, $sp, $imm", []>;
+ IIC_iALUi, "subw", "\t$dst, $sp, $imm", []>;
// SUB r, sp, so_reg
def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
IIC_iALUsi,
- "sub", " $dst, $sp, $rhs", []>;
+ "sub", "\t$dst, $sp, $rhs", []>;
// Pseudo instruction that will expand into a t2SUBrSPi + a copy.
let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
- NoItinerary, "@ sub.w $dst, $sp, $imm", []>;
+ NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>;
def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
- NoItinerary, "@ subw $dst, $sp, $imm", []>;
+ NoItinerary, "@ subw\t$dst, $sp, $imm", []>;
def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
- NoItinerary, "@ sub $dst, $sp, $rhs", []>;
+ NoItinerary, "@ sub\t$dst, $sp, $rhs", []>;
} // usesCustomDAGSchedInserter
@@ -484,10 +484,10 @@
// Load doubleword
def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2),
(ins t2addrmode_imm8s4:$addr),
- IIC_iLoadi, "ldrd", " $dst1, $addr", []>;
+ IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
def t2LDRDpci : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2),
(ins i32imm:$addr), IIC_iLoadi,
- "ldrd", " $dst1, $addr", []>;
+ "ldrd", "\t$dst1, $addr", []>;
}
// zextload i1 -> zextload i8
@@ -535,57 +535,57 @@
def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
- "ldr", " $dst, $addr!", "$addr.base = $base_wb",
+ "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
[]>;
def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
- "ldr", " $dst, [$base], $offset", "$base = $base_wb",
+ "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
[]>;
def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
- "ldrb", " $dst, $addr!", "$addr.base = $base_wb",
+ "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
[]>;
def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
- "ldrb", " $dst, [$base], $offset", "$base = $base_wb",
+ "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
[]>;
def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
- "ldrh", " $dst, $addr!", "$addr.base = $base_wb",
+ "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
[]>;
def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
- "ldrh", " $dst, [$base], $offset", "$base = $base_wb",
+ "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
[]>;
def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
- "ldrsb", " $dst, $addr!", "$addr.base = $base_wb",
+ "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
[]>;
def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
- "ldrsb", " $dst, [$base], $offset", "$base = $base_wb",
+ "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
[]>;
def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
- "ldrsh", " $dst, $addr!", "$addr.base = $base_wb",
+ "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
[]>;
def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
- "ldrsh", " $dst, [$base], $offset", "$base = $base_wb",
+ "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
[]>;
}
@@ -598,48 +598,48 @@
let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
def t2STRDi8 : T2Ii8s4<(outs),
(ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
- IIC_iStorer, "strd", " $src1, $addr", []>;
+ IIC_iStorer, "strd", "\t$src1, $addr", []>;
// Indexed stores
def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
- "str", " $src, [$base, $offset]!", "$base = $base_wb",
+ "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb,
(pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
- "str", " $src, [$base], $offset", "$base = $base_wb",
+ "str", "\t$src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb,
(post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
- "strh", " $src, [$base, $offset]!", "$base = $base_wb",
+ "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb,
(pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
- "strh", " $src, [$base], $offset", "$base = $base_wb",
+ "strh", "\t$src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb,
(post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
- "strb", " $src, [$base, $offset]!", "$base = $base_wb",
+ "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb,
(pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
- "strb", " $src, [$base], $offset", "$base = $base_wb",
+ "strb", "\t$src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb,
(post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
@@ -653,12 +653,12 @@
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
def t2LDM : T2XI<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
- IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide} $addr, $wb", []>;
+ IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", []>;
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
def t2STM : T2XI<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
- IIC_iStorem, "stm${addr:submode}${p}${addr:wide} $addr, $wb", []>;
+ IIC_iStorem, "stm${addr:submode}${p}${addr:wide}\t$addr, $wb", []>;
//===----------------------------------------------------------------------===//
// Move Instructions.
@@ -666,22 +666,22 @@
let neverHasSideEffects = 1 in
def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
- "mov", ".w $dst, $src", []>;
+ "mov", ".w\t$dst, $src", []>;
// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
- "mov", ".w $dst, $src",
+ "mov", ".w\t$dst, $src",
[(set GPR:$dst, t2_so_imm:$src)]>;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
- "movw", " $dst, $src",
+ "movw", "\t$dst, $src",
[(set GPR:$dst, imm0_65535:$src)]>;
let Constraints = "$src = $dst" in
def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
- "movt", " $dst, $imm",
+ "movt", "\t$dst, $imm",
[(set GPR:$dst,
(or (and GPR:$src, 0xffff), lo16AllZero:$imm))]>;
@@ -760,16 +760,16 @@
let Uses = [CPSR] in {
def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
- "rrx", " $dst, $src",
+ "rrx", "\t$dst, $src",
[(set GPR:$dst, (ARMrrx GPR:$src))]>;
}
let Defs = [CPSR] in {
def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
- "lsrs.w $dst, $src, #1",
+ "lsrs.w\t$dst, $src, #1",
[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
- "asrs.w $dst, $src, #1",
+ "asrs.w\t$dst, $src, #1",
[(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
}
@@ -785,14 +785,14 @@
let Constraints = "$src = $dst" in
def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
- IIC_iALUi, "bfc", " $dst, $imm",
+ IIC_iALUi, "bfc", "\t$dst, $imm",
[(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
- IIC_iALUi, "sbfx", " $dst, $src, $lsb, $width", []>;
+ IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []>;
def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
- IIC_iALUi, "ubfx", " $dst, $src, $lsb, $width", []>;
+ IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []>;
// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
@@ -819,80 +819,80 @@
//
let isCommutable = 1 in
def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
- "mul", " $dst, $a, $b",
+ "mul", "\t$dst, $a, $b",
[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
- "mla", " $dst, $a, $b, $c",
+ "mla", "\t$dst, $a, $b, $c",
[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
- "mls", " $dst, $a, $b, $c",
+ "mls", "\t$dst, $a, $b, $c",
[(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
// Extra precision multiplies with low / high results
let neverHasSideEffects = 1 in {
let isCommutable = 1 in {
def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
- "smull", " $ldst, $hdst, $a, $b", []>;
+ "smull", "\t$ldst, $hdst, $a, $b", []>;
def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
- "umull", " $ldst, $hdst, $a, $b", []>;
+ "umull", "\t$ldst, $hdst, $a, $b", []>;
}
// Multiply + accumulate
def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
- "smlal", " $ldst, $hdst, $a, $b", []>;
+ "smlal", "\t$ldst, $hdst, $a, $b", []>;
def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
- "umlal", " $ldst, $hdst, $a, $b", []>;
+ "umlal", "\t$ldst, $hdst, $a, $b", []>;
def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
- "umaal", " $ldst, $hdst, $a, $b", []>;
+ "umaal", "\t$ldst, $hdst, $a, $b", []>;
} // neverHasSideEffects
// Most significant word multiply
def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
- "smmul", " $dst, $a, $b",
+ "smmul", "\t$dst, $a, $b",
[(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
- "smmla", " $dst, $a, $b, $c",
+ "smmla", "\t$dst, $a, $b, $c",
[(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
- "smmls", " $dst, $a, $b, $c",
+ "smmls", "\t$dst, $a, $b, $c",
[(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
multiclass T2I_smul<string opc, PatFrag opnode> {
def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
- !strconcat(opc, "bb"), " $dst, $a, $b",
+ !strconcat(opc, "bb"), "\t$dst, $a, $b",
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
(sext_inreg GPR:$b, i16)))]>;
def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
- !strconcat(opc, "bt"), " $dst, $a, $b",
+ !strconcat(opc, "bt"), "\t$dst, $a, $b",
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
(sra GPR:$b, (i32 16))))]>;
def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
- !strconcat(opc, "tb"), " $dst, $a, $b",
+ !strconcat(opc, "tb"), "\t$dst, $a, $b",
[(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
(sext_inreg GPR:$b, i16)))]>;
def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
- !strconcat(opc, "tt"), " $dst, $a, $b",
+ !strconcat(opc, "tt"), "\t$dst, $a, $b",
[(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
(sra GPR:$b, (i32 16))))]>;
def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
- !strconcat(opc, "wb"), " $dst, $a, $b",
+ !strconcat(opc, "wb"), "\t$dst, $a, $b",
[(set GPR:$dst, (sra (opnode GPR:$a,
(sext_inreg GPR:$b, i16)), (i32 16)))]>;
def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
- !strconcat(opc, "wt"), " $dst, $a, $b",
+ !strconcat(opc, "wt"), "\t$dst, $a, $b",
[(set GPR:$dst, (sra (opnode GPR:$a,
(sra GPR:$b, (i32 16))), (i32 16)))]>;
}
@@ -900,33 +900,33 @@
multiclass T2I_smla<string opc, PatFrag opnode> {
def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
- !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
+ !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc,
(opnode (sext_inreg GPR:$a, i16),
(sext_inreg GPR:$b, i16))))]>;
def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
- !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
+ !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
(sra GPR:$b, (i32 16)))))]>;
def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
- !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
+ !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
(sext_inreg GPR:$b, i16))))]>;
def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
- !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
+ !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
(sra GPR:$b, (i32 16)))))]>;
def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
- !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
+ !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
(sext_inreg GPR:$b, i16)), (i32 16))))]>;
def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
- !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
+ !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
(sra GPR:$b, (i32 16))), (i32 16))))]>;
}
@@ -943,15 +943,15 @@
//
def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
- "clz", " $dst, $src",
+ "clz", "\t$dst, $src",
[(set GPR:$dst, (ctlz GPR:$src))]>;
def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
- "rev", ".w $dst, $src",
+ "rev", ".w\t$dst, $src",
[(set GPR:$dst, (bswap GPR:$src))]>;
def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
- "rev16", ".w $dst, $src",
+ "rev16", ".w\t$dst, $src",
[(set GPR:$dst,
(or (and (srl GPR:$src, (i32 8)), 0xFF),
(or (and (shl GPR:$src, (i32 8)), 0xFF00),
@@ -959,14 +959,14 @@
(and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
- "revsh", ".w $dst, $src",
+ "revsh", ".w\t$dst, $src",
[(set GPR:$dst,
(sext_inreg
(or (srl (and GPR:$src, 0xFF00), (i32 8)),
(shl GPR:$src, (i32 8))), i16))]>;
def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
- IIC_iALUsi, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
+ IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
(and (shl GPR:$src2, (i32 imm:$shamt)),
0xFFFF0000)))]>;
@@ -978,7 +978,7 @@
(t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
- IIC_iALUsi, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
+ IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
(and (sra GPR:$src2, imm16_31:$shamt),
0xFFFF)))]>;
@@ -1025,26 +1025,26 @@
// FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :(
def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
- "mov", ".w $dst, $true",
+ "mov", ".w\t$dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
- IIC_iCMOVi, "mov", ".w $dst, $true",
+ IIC_iCMOVi, "mov", ".w\t$dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
def t2MOVCClsl : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
- IIC_iCMOVsi, "lsl", ".w $dst, $true, $rhs", []>,
+ IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">;
def t2MOVCClsr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
- IIC_iCMOVsi, "lsr", ".w $dst, $true, $rhs", []>,
+ IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">;
def t2MOVCCasr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
- IIC_iCMOVsi, "asr", ".w $dst, $true, $rhs", []>,
+ IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">;
def t2MOVCCror : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
- IIC_iCMOVsi, "ror", ".w $dst, $true, $rhs", []>,
+ IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">;
//===----------------------------------------------------------------------===//
@@ -1055,7 +1055,7 @@
let isCall = 1,
Defs = [R0, R12, LR, CPSR] in {
def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
- "bl __aeabi_read_tp",
+ "bl\t__aeabi_read_tp",
[(set R0, ARMthread_pointer)]>;
}
@@ -1078,13 +1078,13 @@
D31 ] in {
def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src),
AddrModeNone, SizeSpecial, NoItinerary,
- "str.w sp, [$src, #+8] @ eh_setjmp begin\n"
- "\tadr r12, 0f\n"
- "\torr r12, #1\n"
- "\tstr.w r12, [$src, #+4]\n"
- "\tmovs r0, #0\n"
- "\tb 1f\n"
- "0:\tmovs r0, #1 @ eh_setjmp end\n"
+ "str.w\tsp, [$src, #+8] @ eh_setjmp begin\n"
+ "\tadr\tr12, 0f\n"
+ "\torr\tr12, #1\n"
+ "\tstr.w\tr12, [$src, #+4]\n"
+ "\tmovs\tr0, #0\n"
+ "\tb\t1f\n"
+ "0:\tmovs\tr0, #1 @ eh_setjmp end\n"
"1:", "",
[(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
}
@@ -1103,32 +1103,32 @@
hasExtraDefRegAllocReq = 1 in
def t2LDM_RET : T2XI<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
- IIC_Br, "ldm${addr:submode}${p}${addr:wide} $addr, $wb",
+ IIC_Br, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb",
[]>;
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
let isPredicable = 1 in
def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
- "b.w $target",
+ "b.w\t$target",
[(br bb:$target)]>;
let isNotDuplicable = 1, isIndirectBranch = 1 in {
def t2BR_JT :
T2JTI<(outs),
(ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
- IIC_Br, "mov pc, $target\n$jt",
+ IIC_Br, "mov\tpc, $target\n$jt",
[(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
// FIXME: Add a non-pc based case that can be predicated.
def t2TBB :
T2JTI<(outs),
(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
- IIC_Br, "tbb $index\n$jt", []>;
+ IIC_Br, "tbb\t$index\n$jt", []>;
def t2TBH :
T2JTI<(outs),
(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
- IIC_Br, "tbh $index\n$jt", []>;
+ IIC_Br, "tbh\t$index\n$jt", []>;
} // isNotDuplicable, isIndirectBranch
} // isBranch, isTerminator, isBarrier
@@ -1137,14 +1137,14 @@
// a two-value operand where a dag node expects two operands. :(
let isBranch = 1, isTerminator = 1 in
def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
- "b", ".w $target",
+ "b", ".w\t$target",
[/*(ARMbrcond bb:$target, imm:$cc)*/]>;
// IT block
def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
AddrModeNone, Size2Bytes, IIC_iALUx,
- "it$mask $cc", "", []>;
+ "it$mask\t$cc", "", []>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
@@ -1175,5 +1175,5 @@
// when we can do generalized remat.
let isReMaterializable = 1 in
def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
- "movw", " $dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
+ "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
[(set GPR:$dst, (i32 imm:$src))]>;
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