[llvm-commits] Added more 's' bit set encoding and "rs" register encoding bits

[Evan Cheng]

On Oct 26, 2009, at 3:34 PM, Bob Wilson wrote:

> As far as I can tell, the lack of predication for ADC/SBC is a  
> temporary limitation in llvm.  Evan, can you confirm?

Right.

> 
> I've applied the rest of the patch for now, without the change to  
> force the condition fields.  That should be done as a separate patch  
> anyway, since it is unrelated to this change.

Are you guys making sure the ARM JIT is still working correctly after these series of encoding changes?

Evan

> 
> On Oct 26, 2009, at 11:48 AM, Johnny Chen wrote:
> 
>> Hi,
>> 
>> For multiclass AI1_adde_sube_irs definition, I also added:
>> 
>>   let Inst{31-28} = 0b1110;
>> 
>> for the Sri, Srr, and Srs variants.  From the AsmString field of the  
>> respective record definitions
>> (take SBCSrs, for example):
>> 
>> string AsmString = "sbcs $dst, $a, $b";
>> 
>> it looks like this is the right thing to do.  Please remove the  
>> three "set condition code to ALways"
>> lines from the submitted patch if this is not correct.
>> 
>> Thanks.
>> 
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