[llvm-commits] Added more 's' bit set encoding and "rs" register encoding bits

[Johnny Chen]

Hi,

For multiclass AI1_adde_sube_irs definition, I also added:

    let Inst{31-28} = 0b1110;

for the Sri, Srr, and Srs variants.  From the AsmString field of the respective record definitions
(take SBCSrs, for example):

string AsmString = "sbcs $dst, $a, $b";

it looks like this is the right thing to do.  Please remove the three "set condition code to ALways"
lines from the submitted patch if this is not correct.

Thanks.

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