[llvm-commits] [llvm] r84868 - in /llvm/trunk: lib/Target/ARM/ARMTargetMachine.cpp test/CodeGen/ARM/ifcvt5.ll

[Evan Cheng]

Yes sorry. I was going to revert it myself. The problem is post-regalloc scheduling can change register allocation. That doesn't work for diamond shape if-conversion when two instructions with mutually exclusive predicates must target the same register.

Evan

On Oct 22, 2009, at 9:52 AM, Bob Wilson wrote:

> Author: bwilson
> Date: Thu Oct 22 11:52:21 2009
> New Revision: 84868
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=84868&view=rev
> Log:
> Revert 84843.  Evan, this was breaking some of the if-conversion tests.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
>    llvm/trunk/test/CodeGen/ARM/ifcvt5.ll
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=84868&r1=84867&r2=84868&view=diff
> 
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Oct 22 11:52:21 2009
> @@ -103,16 +103,18 @@
> bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
>                                         CodeGenOpt::Level OptLevel) {
>   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
> -  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) {
> +  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
>     PM.add(createARMLoadStoreOptimizationPass());
> -    PM.add(createIfConverterPass());
> -  }
> 
>   return true;
> }
> 
> bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
>                                           CodeGenOpt::Level OptLevel) {
> +  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
> +  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
> +    PM.add(createIfConverterPass());
> +
>   if (Subtarget.isThumb2()) {
>     PM.add(createThumb2ITBlockPass());
>     PM.add(createThumb2SizeReductionPass());
> 
> Modified: llvm/trunk/test/CodeGen/ARM/ifcvt5.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt5.ll?rev=84868&r1=84867&r2=84868&view=diff
> 
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/ifcvt5.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/ifcvt5.ll Thu Oct 22 11:52:21 2009
> @@ -11,8 +11,7 @@
> 
> define void @t1(i32 %a, i32 %b) {
> ; CHECK: t1:
> -; CHECK: movge
> -; CHECK: blge _foo
> +; CHECK: ldmltfd sp!, {r7, pc}
> entry:
> 	%tmp1 = icmp sgt i32 %a, 10		; <i1> [#uses=1]
> 	br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
> 
> 
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