[llvm-commits] [llvm] r84843 - in /llvm/trunk: lib/Target/ARM/ARMTargetMachine.cpp test/CodeGen/ARM/ifcvt5.ll

[Evan Cheng]

Author: evancheng
Date: Thu Oct 22 01:48:32 2009
New Revision: 84843

URL: http://llvm.org/viewvc/llvm-project?rev=84843&view=rev
Log:
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.

Modified:
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
    llvm/trunk/test/CodeGen/ARM/ifcvt5.ll

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=84843&r1=84842&r2=84843&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Oct 22 01:48:32 2009
@@ -103,18 +103,16 @@
 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
                                         CodeGenOpt::Level OptLevel) {
   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
-  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
+  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) {
     PM.add(createARMLoadStoreOptimizationPass());
+    PM.add(createIfConverterPass());
+  }
 
   return true;
 }
 
 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
                                           CodeGenOpt::Level OptLevel) {
-  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
-  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
-    PM.add(createIfConverterPass());
-
   if (Subtarget.isThumb2()) {
     PM.add(createThumb2ITBlockPass());
     PM.add(createThumb2SizeReductionPass());

Modified: llvm/trunk/test/CodeGen/ARM/ifcvt5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt5.ll?rev=84843&r1=84842&r2=84843&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt5.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt5.ll Thu Oct 22 01:48:32 2009
@@ -11,7 +11,8 @@
 
 define void @t1(i32 %a, i32 %b) {
 ; CHECK: t1:
-; CHECK: ldmltfd sp!, {r7, pc}
+; CHECK: movge
+; CHECK: blge _foo
 entry:
 	%tmp1 = icmp sgt i32 %a, 10		; <i1> [#uses=1]
 	br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock