[llvm-commits] [llvm] r83768 - /llvm/trunk/docs/ReleaseNotes-2.6.html

Gabor Greif ggreif at gmail.com
Sun Oct 11 03:27:58 PDT 2009


Author: ggreif
Date: Sun Oct 11 05:27:57 2009
New Revision: 83768

URL: http://llvm.org/viewvc/llvm-project?rev=83768&view=rev
Log:
fix some obvious typos

Modified:
    llvm/trunk/docs/ReleaseNotes-2.6.html

Modified: llvm/trunk/docs/ReleaseNotes-2.6.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes-2.6.html?rev=83768&r1=83767&r2=83768&view=diff

==============================================================================
--- llvm/trunk/docs/ReleaseNotes-2.6.html (original)
+++ llvm/trunk/docs/ReleaseNotes-2.6.html Sun Oct 11 05:27:57 2009
@@ -650,7 +650,7 @@
     from the compiler.  It works well for many simple C testcases, but doesn't
     support exception handling, debug info, inline assembly, etc.</li>
 <li>Targets can now specify register allocation hints through
-    MachineRegisterInfo:: setRegAllocationHint. A regalloc hint consists of hint
+    MachineRegisterInfo::setRegAllocationHint. A regalloc hint consists of hint
     type and physical register number. A hint type of zero specifies a register
     allocation preference. Other hint type values are target specific which are
     resolved by TargetRegisterInfo::ResolveRegAllocHint. An example is the ARM
@@ -675,7 +675,7 @@
     by OS kernels.</li>
 <li>X86-64 now models implicit zero extensions better, which allows the code
     generator to remove a lot of redundant zexts.  It also models the 8-bit "H"
-    registers as sugregs, which allows they to be used in some tricky
+    registers as sugregs, which allows them to be used in some tricky
     situations.</li>
 <li>X86-64 now supports the "local exec" and "initial exec" thread local storage
     model.</li>
@@ -741,8 +741,8 @@
 <li>The AAPCS-VFP "hard float" calling conventions are also supported with the
 <tt>-float-abi=hard</tt> flag.</li>
 
-<li>The ARM calling convention code is now tblgen generated instead of C++
-    code.</li>
+<li>The ARM calling convention code is now tblgen generated instead of resorting
+    to C++ code.</li>
 </li>
 
 





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