[llvm-commits] [llvm] r83467 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/
Evan Cheng
evan.cheng at apple.com
Wed Oct 7 16:48:41 PDT 2009
On Oct 7, 2009, at 12:12 PM, Jim Grosbach wrote:
>
> On Oct 7, 2009, at 11:38 AM, Evan Cheng wrote:
>
>>
>> On Oct 7, 2009, at 10:12 AM, Jim Grosbach wrote:
>>
>>> Author: grosbach
>>> Date: Wed Oct 7 12:12:56 2009
>>> New Revision: 83467
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=83467&view=rev
>>> Log:
>>> Add register-reuse to frame-index register scavenging. When a
>>> target uses
>>> a virtual register to eliminate a frame index, it can return that
>>> register
>>> and the constant stored there to PEI to track. When scavenging to
>>> allocate
>>> for those registers, PEI then tracks the last-used register and
>>> value, and
>>> if it is still available and matches the value for the next index,
>>> reuses
>>> the existing value rather and removes the re-materialization
>>> instructions.
>>> Fancier tracking and adjustment of scavenger allocations to keep
>>> more
>>> values live for longer is possible, but not yet implemented and
>>> would likely
>>> be better done via a different, less special-purpose, approach to
>>> the
>>> problem.
>>
>> Hi Jim,
>>
>> Is PEI responsible for allocating physical registers to the virtual
>> registers created during eliminateFrameIndex()? That's ok for now.
>> But the question is when that is moved to a separate pass does this
>> reuse scheme still work?
>
> The allocation is currently done in PEI, yes. There's nothing
> preventing moving it out; however, with a bit of analysis data
> passed between them.
>
>>
>> More comments below.
>>
>> Evan
>>
>>>
>>> eliminateFrameIndex() is modified so the target implementations
>>> can return
>>> the registers they wish to be tracked for reuse.
>>>
>>> ARM Thumb1 implements and utilizes the new mechanism. All other
>>> targets are
>>> simply modified to adjust for the changed eliminateFrameIndex()
>>> prototype.
>>>
>>>
>>> Modified:
>>> llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h
>>> llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
>>> llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
>>> llvm/trunk/lib/CodeGen/PrologEpilogInserter.h
>>> llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
>>> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
>>> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
>>> llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
>>> llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h
>>> llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
>>> llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h
>>> llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
>>> llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h
>>> llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
>>> llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
>>> llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
>>> llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h
>>> llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
>>> llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
>>> llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.cpp
>>> llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.h
>>> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
>>> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
>>> llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
>>> llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
>>> llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
>>> llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
>>> llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
>>> llvm/trunk/lib/Target/X86/X86RegisterInfo.h
>>> llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
>>> llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h Wed Oct
>>> 7 12:12:56 2009
>>> @@ -117,6 +117,9 @@
>>> return scavengeRegister(RegClass, MBBI, SPAdj);
>>> }
>>>
>>> + /// setUsed - Tell the scavenger a register is used.
>>> + ///
>>> + void setUsed(unsigned Reg);
>>
>> I'd prefer not to do this if it can be helped. RS should be
>> entirely responsible for tracking the liveness. Why is this needed?
>
> When we recognize that we can reuse a register, we reach back to the
> previously killing use and clear the kill flag, since the live range
> for the register has been extended. The scavenger state needs to be
> updated to know that the register still have a live value in it at
> this point, so we also need to flag it as used. Otherwise, the
> scavenger state isn't reflective of the new code.
Ok. How about changing it to extendLiveness() to make it more explicit
what's happening?
>
>>
>>> private:
>>> /// isReserved - Returns true if a register is reserved. It is
>>> never "unused".
>>> bool isReserved(unsigned Reg) const { return ReservedRegs.test
>>> (Reg); }
>>> @@ -131,7 +134,6 @@
>>>
>>> /// setUsed / setUnused - Mark the state of one or a number of
>>> registers.
>>> ///
>>> - void setUsed(unsigned Reg);
>>> void setUsed(BitVector &Regs) {
>>> RegsAvailable &= ~Regs;
>>> }
>>>
>>> Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
>>> +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -660,8 +660,13 @@
>>> /// specified instruction, as long as it keeps the iterator
>>> pointing the the
>>> /// finished product. SPAdj is the SP adjustment due to call frame
>>> setup
>>> /// instruction.
>>> - virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
>>> - int SPAdj, RegScavenger
>>> *RS=NULL) const = 0;
>>> + ///
>>> + /// When -enable-frame-index-scavenging is enabled, the virtual
>>> register
>>> + /// allocated for this frame index is returned and its value is
>>> stored in
>>> + /// *Value.
>>> + virtual unsigned eliminateFrameIndex
>>> (MachineBasicBlock::iterator MI,
>>> + int SPAdj, int *Value =
>>> NULL,
>>> + RegScavenger *RS=NULL)
>>> const = 0;
>>>
>>> /// emitProlog/emitEpilog - These methods insert prolog and epilog
>>> code into
>>> /// the function.
>>>
>>> Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -655,6 +655,11 @@
>>> int FrameSetupOpcode = TRI.getCallFrameSetupOpcode();
>>> int FrameDestroyOpcode = TRI.getCallFrameDestroyOpcode();
>>>
>>> + // Pre-allocate space for frame index mappings. If more space
>>> is needed,
>>> + // the map will be grown later.
>>> + if (FrameIndexVirtualScavenging)
>>> + FrameConstantRegMap.grow(Fn.getRegInfo().getLastVirtReg() +
>>> 128);
>>> +
>>> for (MachineFunction::iterator BB = Fn.begin(),
>>> E = Fn.end(); BB != E; ++BB) {
>>> int SPAdj = 0; // SP offset due to call frame setup / destroy.
>>> @@ -703,9 +708,17 @@
>>> // If this instruction has a FrameIndex operand, we need to
>>> // use that target machine register info object to eliminate
>>> // it.
>>> -
>>> - TRI.eliminateFrameIndex(MI, SPAdj,
>>> FrameIndexVirtualScavenging ?
>>> - NULL : RS);
>>> + int Value;
>>> + unsigned VReg =
>>> + TRI.eliminateFrameIndex(MI, SPAdj, &Value,
>>> +
>>> FrameIndexVirtualScavenging ? NULL : RS);
>>> + if (VReg) {
>>> + assert (FrameIndexVirtualScavenging &&
>>> + "Not scavenging, but virtual returned from "
>>> + "eliminateFrameIndex()!");
>>> + FrameConstantRegMap.grow(VReg);
>>> + FrameConstantRegMap[VReg] = FrameConstantEntry(Value,
>>> SPAdj);
>>> + }
>>>
>>> // Reset the iterator if we were at the beginning of the BB.
>>> if (AtBeginning) {
>>> @@ -727,6 +740,35 @@
>>> }
>>> }
>>>
>>> +/// findLastUseReg - find the killing use of the specified
>>> register within
>>> +/// the instruciton range. Return the operand number of the kill
>>> in Operand.
>>> +static MachineBasicBlock::iterator
>>> +findLastUseReg(MachineBasicBlock::iterator I,
>>> MachineBasicBlock::iterator ME,
>>> + unsigned Reg, unsigned *Operand) {
>>> + // Scan forward to find the last use of this virtual register
>>> + for (++I; I != ME; ++I) {
>>> + MachineInstr *MI = I;
>>> + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
>>> + if (MI->getOperand(i).isReg()) {
>>> + unsigned OpReg = MI->getOperand(i).getReg();
>>> + if (OpReg == 0 || !TargetRegisterInfo::isVirtualRegister
>>> (OpReg))
>>> + continue;
>>> + assert (OpReg == Reg
>>> + && "overlapping use of scavenged index register!");
>>> + // If this is the killing use, we're done
>>> + if (MI->getOperand(i).isKill()) {
>>> + if (Operand)
>>> + *Operand = i;
>>> + return I;
>>> + }
>>> + }
>>> + }
>>> + // If we hit the end of the basic block, there was no kill of
>>> + // the virtual register, which is wrong.
>>> + assert (0 && "scavenged index register never killed!");
>>> + return ME;
>>> +}
>>> +
>>> /// scavengeFrameVirtualRegs - Replace all frame index virtual
>>> registers
>>> /// with physical registers. Use the register scavenger to find an
>>> /// appropriate register to use.
>>> @@ -738,12 +780,21 @@
>>>
>>> unsigned CurrentVirtReg = 0;
>>> unsigned CurrentScratchReg = 0;
>>> + unsigned PrevScratchReg = 0;
>>> + int PrevValue;
>>> + MachineInstr *PrevLastUseMI;
>>> + unsigned PrevLastUseOp;
>>>
>>> + // The instruction stream may change in the loop, so check BB-
>>> >end()
>>> + // directly.
>>> for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end();
>>> ++I) {
>>> MachineInstr *MI = I;
>>> - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
>>> + // Likewise, call getNumOperands() each iteration, as the
>>> MI may change
>>> + // inside the loop (with 'i' updated accordingly).
>>
>> Why not just re-compute the end limit when MI is updated?
>
> We could. To me the code just reads more clearly this way. i.e.,
> stylistic choice. If you prefer, I'll change it. No big deal to me
> either way.
I'd prefer not to recompute getNumOperands() everytime, thanks.
>
>>
>>> + for (unsigned i = 0; i != MI->getNumOperands(); ++i)
>>> if (MI->getOperand(i).isReg()) {
>>> - unsigned Reg = MI->getOperand(i).getReg();
>>> + MachineOperand &MO = MI->getOperand(i);
>>> + unsigned Reg = MO.getReg();
>>> if (Reg == 0)
>>> continue;
>>> if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
>>> @@ -751,33 +802,81 @@
>>> // seeing any references to it.
>>> assert (Reg != CurrentScratchReg
>>> && "overlapping use of scavenged frame index
>>> register!");
>>> +
>>> + // If we have a previous scratch reg, check and see
>>> if anything
>>> + // here kills whatever value is in there.
>>> + if (Reg == PrevScratchReg) {
>>> + if (MO.isUse()) {
>>> + // Two-address operands implicitly kill
>>> + if (MO.isKill() || MI->isRegTiedToDefOperand(i))
>>> + PrevScratchReg = 0;
>>> + } else {
>>> + assert (MO.isDef());
>>> + PrevScratchReg = 0;
>>> + }
>>> + }
>>> continue;
>>> }
>>>
>>> // If we already have a scratch for this virtual register,
>>> use it
>>> if (Reg != CurrentVirtReg) {
>>> - // When we first encounter a new virtual register, it
>>> - // must be a definition.
>>> - assert(MI->getOperand(i).isDef() &&
>>> - "frame index virtual missing def!");
>>> - // We can't have nested virtual register live ranges
>>> because
>>> - // there's only a guarantee of one scavenged register
>>> at a time.
>>> - assert (CurrentVirtReg == 0 &&
>>> - "overlapping frame index virtual registers!");
>>> - CurrentVirtReg = Reg;
>>> - const TargetRegisterClass *RC = Fn.getRegInfo
>>> ().getRegClass(Reg);
>>> - CurrentScratchReg = RS->FindUnusedReg(RC);
>>> - if (CurrentScratchReg == 0)
>>> - // No register is "free". Scavenge a register.
>>> - // FIXME: Track SPAdj. Zero won't always be right
>>> - CurrentScratchReg = RS->scavengeRegister(RC, I, 0);
>>> + int Value = FrameConstantRegMap[Reg].first;
>>> + int SPAdj = FrameConstantRegMap[Reg].second;
>>> +
>>> + // If the scratch register from the last allocation
>>> is still
>>> + // available, see if the value matches. If it does,
>>> just re-use it.
>>> + if (PrevScratchReg && Value == PrevValue) {
>>
>> This means the reuse can only happen when you have consecutive uses
>> of the same frame indices. That seems very restrictive. The
>> implementation makes it difficult to separate the allocation phase
>> from PEI.
>
> The former is currently true, yes. It seemed a reasonable subset of
> the general problem to solve. Doing more would require tracking the
> liveness of multiple values, and I'm concerned about worst case
> performance if I do too much of that sort of thing when iterating
> over the instruction list.
>
> I'm not sure I follow why it is more difficult to separate into
> another pass due to implementation. There are some inherent
> complications that make it tricky, however, yes. Specifically, I
> think the constant value references need help from the target. I'll
> think about this a bit more and see if that's always true, or if
> there's something we can do about it. If that can be simplified, it
> would be great.
If you don't think it's difficult to separate it into a pass, I'm ok
with leaving it as it is for now. We can talk about the design offline.
Evan
>
>>
>>
>>> + // FIXME: This assumes that the instructions in the
>>> live range
>>> + // for the virtual register are exclusively for the
>>> purpose
>>> + // of populating the value in the register. That
>>> reasonable
>>
>> That -> That's.
>
> Woops. Thanks. Fixed.
>
>>
>>> + // for these frame index registers, but it's still
>>> a very, very
>>> + // strong assumption. Perhaps this implies that the
>>> frame index
>>> + // elimination should be before register
>>> allocation, with
>>> + // conservative heuristics since we'll know less
>>> then, and
>>> + // the reuse calculations done directly when doing
>>> the code-gen?
>>
>> This can be solved later.
>
> Agreed. Just putting it as a fixme to remind us.
>
>>
>>> +
>>> + // Find the last use of the new virtual register.
>>> Remove all
>>> + // instruction between here and there, and update
>>> the current
>>> + // instruction to reference the last use insn
>>> instead.
>>> + MachineBasicBlock::iterator LastUseMI =
>>> + findLastUseReg(I, BB->end(), Reg, &i);
>>
>>> + // Remove all instructions up 'til the last use,
>>> since they're
>>> + // just calculating the value we already have.
>>> + BB->erase(I, LastUseMI);
>>> + MI = I = LastUseMI;
>>
>> Rather than doing this, you could simply continue to iterate
>> forward until you have reached the kill.
>
> There's a couple ways I think the code can be adjusted to have a
> cleaner flow. This is definitely a good example.
>
>>
>>> +
>>> + CurrentScratchReg = PrevScratchReg;
>>> + // Extend the live range of the register
>>> + PrevLastUseMI->getOperand(PrevLastUseOp).setIsKill
>>> (false);
>>> + RS->setUsed(CurrentScratchReg);
>>> + } else {
>>> + // When we first encounter a new virtual register, it
>>> + // must be a definition.
>>> + assert(MI->getOperand(i).isDef() &&
>>> + "frame index virtual missing def!");
>>> + // We can't have nested virtual register live
>>> ranges because
>>> + // there's only a guarantee of one scavenged
>>> register at a time.
>>> + assert (CurrentVirtReg == 0 &&
>>> + "overlapping frame index virtual
>>> registers!");
>>> + CurrentVirtReg = Reg;
>>> + const TargetRegisterClass *RC = Fn.getRegInfo
>>> ().getRegClass(Reg);
>>> + CurrentScratchReg = RS->FindUnusedReg(RC);
>>> + if (CurrentScratchReg == 0)
>>> + // No register is "free". Scavenge a register.
>>> + CurrentScratchReg = RS->scavengeRegister(RC, I,
>>> SPAdj);
>>> +
>>> + PrevValue = Value;
>>> + }
>>> }
>>> assert (CurrentScratchReg && "Missing scratch register!");
>>> MI->getOperand(i).setReg(CurrentScratchReg);
>>>
>>> // If this is the last use of the register, stop tracking it.
>>> - if (MI->getOperand(i).isKill())
>>> + if (MI->getOperand(i).isKill()) {
>>> + PrevScratchReg = CurrentScratchReg;
>>> + PrevLastUseMI = MI;
>>> CurrentScratchReg = CurrentVirtReg = 0;
>>> + }
>>> }
>>> RS->forward(MI);
>>> }
>>>
>>> Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.h (original)
>>> +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -27,6 +27,8 @@
>>> #include "llvm/CodeGen/MachineLoopInfo.h"
>>> #include "llvm/ADT/SparseBitVector.h"
>>> #include "llvm/ADT/DenseMap.h"
>>> +#include "llvm/ADT/IndexedMap.h"
>>> +#include "llvm/Target/TargetRegisterInfo.h"
>>>
>>> namespace llvm {
>>> class RegScavenger;
>>> @@ -93,6 +95,12 @@
>>> // functions.
>>> bool ShrinkWrapThisFunction;
>>>
>>> + // When using the scavenger post-pass to resolve frame
>>> reference
>>> + // materialization registers, maintain a map of the registers
>>> to
>>> + // the constant value and SP adjustment associated with it.
>>> + typedef std::pair<int, int> FrameConstantEntry;
>>> + IndexedMap<FrameConstantEntry, VirtReg2IndexFunctor>
>>> FrameConstantRegMap;
>>> +
>>> #ifndef NDEBUG
>>> // Machine function handle.
>>> MachineFunction* MF;
>>>
>>> Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -306,7 +306,7 @@
>>> "Cannot scavenge register without an emergency spill
>>> slot!");
>>> TII->storeRegToStackSlot(*MBB, I, SReg, true,
>>> ScavengingFrameIndex, RC);
>>> MachineBasicBlock::iterator II = prior(I);
>>> - TRI->eliminateFrameIndex(II, SPAdj, this);
>>> + TRI->eliminateFrameIndex(II, SPAdj, NULL, this);
>>>
>>> // Restore the scavenged register before its use (or first
>>> terminator).
>>> TII->loadRegFromStackSlot(*MBB, UseMI, SReg,
>>> ScavengingFrameIndex, RC);
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -1023,9 +1023,10 @@
>>> return Reg;
>>> }
>>>
>>> -void
>>> +unsigned
>>> ARMBaseRegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger
>>> *RS) const {
>>> + int SPAdj, int *Value,
>>> + RegScavenger *RS) const {
>>> unsigned i = 0;
>>> MachineInstr &MI = *II;
>>> MachineBasicBlock &MBB = *MI.getParent();
>>> @@ -1067,7 +1068,7 @@
>>> Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
>>> }
>>> if (Done)
>>> - return;
>>> + return 0;
>>>
>>> // If we get here, the immediate doesn't fit into the
>>> instruction. We folded
>>> // as much as possible above, handle the rest, providing a
>>> register that is
>>> @@ -1102,6 +1103,7 @@
>>> }
>>> MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
>>> }
>>> + return 0;
>>> }
>>>
>>> /// Move iterator pass the next bunch of callee save load / store
>>> ops for
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -128,8 +128,9 @@
>>> MachineBasicBlock &MBB,
>>>
>>> MachineBasicBlock::iterator I) const;
>>>
>>> - virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger *RS =
>>> NULL) const;
>>> + virtual unsigned eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value =
>>> NULL,
>>> + RegScavenger *RS = NULL)
>>> const;
>>>
>>> virtual void emitPrologue(MachineFunction &MF) const;
>>> virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock
>>> &MBB) const;
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -427,8 +427,11 @@
>>> TII.copyRegToReg(MBB, I, Reg, ARM::R12, RC, ARM::GPRRegisterClass);
>>> }
>>>
>>> -void Thumb1RegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> - int SPAdj,
>>> RegScavenger *RS) const{
>>> +unsigned
>>> +Thumb1RegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value,
>>> + RegScavenger *RS) const{
>>> + unsigned VReg = 0;
>>> unsigned i = 0;
>>> MachineInstr &MI = *II;
>>> MachineBasicBlock &MBB = *MI.getParent();
>>> @@ -484,7 +487,7 @@
>>> MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
>>> MI.getOperand(i).ChangeToRegister(FrameReg, false);
>>> MI.RemoveOperand(i+1);
>>> - return;
>>> + return 0;
>>> }
>>>
>>> // Common case: small offset, fits into instruction.
>>> @@ -500,7 +503,7 @@
>>> MI.getOperand(i).ChangeToRegister(FrameReg, false);
>>> MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
>>> }
>>> - return;
>>> + return 0;
>>> }
>>>
>>> unsigned DestReg = MI.getOperand(0).getReg();
>>> @@ -512,7 +515,7 @@
>>> emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset,
>>> TII,
>>> *this, dl);
>>> MBB.erase(II);
>>> - return;
>>> + return 0;
>>> }
>>>
>>> if (Offset > 0) {
>>> @@ -545,7 +548,7 @@
>>> AddDefaultPred(MIB);
>>> }
>>> }
>>> - return;
>>> + return 0;
>>> } else {
>>> unsigned ImmIdx = 0;
>>> int InstrOffs = 0;
>>> @@ -575,7 +578,7 @@
>>> // Replace the FrameIndex with sp
>>> MI.getOperand(i).ChangeToRegister(FrameReg, false);
>>> ImmOp.ChangeToImmediate(ImmedOffset);
>>> - return;
>>> + return 0;
>>> }
>>>
>>> bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode ==
>>> ARM::tSpill;
>>> @@ -633,22 +636,24 @@
>>> MI.addOperand(MachineOperand::CreateReg(0, false));
>>> } else if (Desc.mayStore()) {
>>> if (FrameIndexVirtualScavenging) {
>>> - unsigned TmpReg =
>>> - MF.getRegInfo().createVirtualRegister
>>> (ARM::tGPRRegisterClass);
>>> + VReg = MF.getRegInfo().createVirtualRegister
>>> (ARM::tGPRRegisterClass);
>>> + assert (Value && "Frame index virtual allocated, but Value
>>> arg is NULL!");
>>> + *Value = Offset;
>>> bool UseRR = false;
>>> +
>>> if (Opcode == ARM::tSpill) {
>>> if (FrameReg == ARM::SP)
>>> - emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
>>> + emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
>>> Offset, false, TII, *this, dl);
>>> else {
>>> - emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
>>> + emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
>>> UseRR = true;
>>> }
>>> } else
>>> - emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg,
>>> Offset, TII,
>>> + emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg,
>>> Offset, TII,
>>> *this, dl);
>>> MI.setDesc(TII.get(ARM::tSTR));
>>> - MI.getOperand(i).ChangeToRegister(TmpReg, false, false,
>>> true);
>>> + MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
>>> if (UseRR) // Use [reg, reg] addrmode.
>>> MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
>>> else // tSTR has an extra register operand.
>>> @@ -707,6 +712,7 @@
>>> MachineInstrBuilder MIB(&MI);
>>> AddDefaultPred(MIB);
>>> }
>>> + return VReg;
>>> }
>>>
>>> void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -62,8 +62,9 @@
>>> MachineBasicBlock::iterator I,
>>> const TargetRegisterClass *RC,
>>> unsigned Reg) const;
>>> - void eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger *RS = NULL)
>>> const;
>>> + unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value = NULL,
>>> + RegScavenger *RS = NULL) const;
>>>
>>> void emitPrologue(MachineFunction &MF) const;
>>> void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB)
>>> const;
>>>
>>> Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -151,8 +151,10 @@
>>> //variable locals
>>> //<- SP
>>>
>>> -void AlphaRegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> - int SPAdj,
>>> RegScavenger *RS) const {
>>> +unsigned
>>> +AlphaRegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value,
>>> + RegScavenger *RS) const {
>>> assert(SPAdj == 0 && "Unexpected");
>>>
>>> unsigned i = 0;
>>> @@ -197,6 +199,7 @@
>>> } else {
>>> MI.getOperand(i).ChangeToImmediate(Offset);
>>> }
>>> + return 0;
>>> }
>>>
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -41,8 +41,9 @@
>>> MachineBasicBlock &MBB,
>>> MachineBasicBlock::iterator I)
>>> const;
>>>
>>> - void eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger *RS = NULL)
>>> const;
>>> + unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value = NULL,
>>> + RegScavenger *RS = NULL) const;
>>>
>>> //void processFunctionBeforeFrameFinalized(MachineFunction &MF)
>>> const;
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Wed
>>> Oct 7 12:12:56 2009
>>> @@ -219,9 +219,10 @@
>>> return Reg;
>>> }
>>>
>>> -void BlackfinRegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> - int SPAdj,
>>> - RegScavenger *RS)
>>> const {
>>> +unsigned
>>> +BlackfinRegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value,
>>> + RegScavenger *RS) const {
>>> MachineInstr &MI = *II;
>>> MachineBasicBlock &MBB = *MI.getParent();
>>> MachineFunction &MF = *MBB.getParent();
>>> @@ -258,20 +259,20 @@
>>> MI.setDesc(TII.get(isStore
>>> ? BF::STORE32p_uimm6m4
>>> : BF::LOAD32p_uimm6m4));
>>> - return;
>>> + return 0;
>>> }
>>> if (BaseReg == BF::FP && isUint<7>(-Offset)) {
>>> MI.setDesc(TII.get(isStore
>>> ? BF::STORE32fp_nimm7m4
>>> : BF::LOAD32fp_nimm7m4));
>>> MI.getOperand(FIPos+1).setImm(-Offset);
>>> - return;
>>> + return 0;
>>> }
>>> if (isInt<18>(Offset)) {
>>> MI.setDesc(TII.get(isStore
>>> ? BF::STORE32p_imm18m4
>>> : BF::LOAD32p_imm18m4));
>>> - return;
>>> + return 0;
>>> }
>>> // Use RegScavenger to calculate proper offset...
>>> MI.dump();
>>> @@ -356,6 +357,7 @@
>>> llvm_unreachable("Cannot eliminate frame index");
>>> break;
>>> }
>>> + return 0;
>>> }
>>>
>>> void BlackfinRegisterInfo::
>>>
>>> Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h Wed Oct
>>> 7 12:12:56 2009
>>> @@ -64,8 +64,9 @@
>>> MachineBasicBlock &MBB,
>>> MachineBasicBlock::iterator I)
>>> const;
>>>
>>> - void eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger *RS = NULL)
>>> const;
>>> + unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value = NULL,
>>> + RegScavenger *RS = NULL) const;
>>>
>>> void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
>>> RegScavenger *RS) const;
>>>
>>> Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -326,9 +326,9 @@
>>> MBB.erase(I);
>>> }
>>>
>>> -void
>>> +unsigned
>>> SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator
>>> II, int SPAdj,
>>> - RegScavenger *RS) const
>>> + int *Value, RegScavenger
>>> *RS) const
>>> {
>>> unsigned i = 0;
>>> MachineInstr &MI = *II;
>>> @@ -371,6 +371,7 @@
>>> } else {
>>> MO.ChangeToImmediate(Offset);
>>> }
>>> + return 0;
>>> }
>>>
>>> /// determineFrameLayout - Determine the size of the frame and
>>> maximum call
>>>
>>> Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -63,8 +63,9 @@
>>> MachineBasicBlock &MBB,
>>> MachineBasicBlock::iterator I)
>>> const;
>>> //! Convert frame indicies into machine operands
>>> - void eliminateFrameIndex(MachineBasicBlock::iterator II, int,
>>> - RegScavenger *RS) const;
>>> + unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> int SPAdj,
>>> + int *Value = NULL,
>>> + RegScavenger *RS = NULL) const;
>>> //! Determine the frame's layour
>>> void determineFrameLayout(MachineFunction &MF) const;
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -147,9 +147,10 @@
>>> MBB.erase(I);
>>> }
>>>
>>> -void
>>> +unsigned
>>> MSP430RegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger
>>> *RS) const {
>>> + int SPAdj, int *Value,
>>> + RegScavenger *RS) const {
>>> assert(SPAdj == 0 && "Unexpected");
>>>
>>> unsigned i = 0;
>>> @@ -187,7 +188,7 @@
>>> MI.getOperand(i).ChangeToRegister(BasePtr, false);
>>>
>>> if (Offset == 0)
>>> - return;
>>> + return 0;
>>>
>>> // We need to materialize the offset via add instruction.
>>> unsigned DstReg = MI.getOperand(0).getReg();
>>> @@ -198,11 +199,12 @@
>>> BuildMI(MBB, next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
>>> .addReg(DstReg).addImm(Offset);
>>>
>>> - return;
>>> + return 0;
>>> }
>>>
>>> MI.getOperand(i).ChangeToRegister(BasePtr, false);
>>> MI.getOperand(i+1).ChangeToImmediate(Offset);
>>> + return 0;
>>> }
>>>
>>> void
>>>
>>> Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -49,8 +49,9 @@
>>> MachineBasicBlock &MBB,
>>> MachineBasicBlock::iterator I)
>>> const;
>>>
>>> - void eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger *RS = NULL)
>>> const;
>>> + unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value = NULL,
>>> + RegScavenger *RS = NULL) const;
>>>
>>> void emitPrologue(MachineFunction &MF) const;
>>> void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB)
>>> const;
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -348,9 +348,9 @@
>>> // FrameIndex represent objects inside a abstract stack.
>>> // We must replace FrameIndex with an stack/frame pointer
>>> // direct reference.
>>> -void MipsRegisterInfo::
>>> -eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
>>> - RegScavenger *RS) const
>>> +unsigned MipsRegisterInfo::
>>> +eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
>>> + int *Value, RegScavenger *RS) const
>>> {
>>> MachineInstr &MI = *II;
>>> MachineFunction &MF = *MI.getParent()->getParent();
>>> @@ -382,6 +382,7 @@
>>>
>>> MI.getOperand(i-1).ChangeToImmediate(Offset);
>>> MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
>>> + return 0;
>>> }
>>>
>>> void MipsRegisterInfo::
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -54,8 +54,9 @@
>>> MachineBasicBlock::iterator I)
>>> const;
>>>
>>> /// Stack Frame Processing Methods
>>> - void eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger *RS = NULL)
>>> const;
>>> + unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value = NULL,
>>> + RegScavenger *RS = NULL) const;
>>>
>>> void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -51,10 +51,13 @@
>>> return false;
>>> }
>>>
>>> -void PIC16RegisterInfo::
>>> +unsigned PIC16RegisterInfo::
>>> eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
>>> - RegScavenger *RS) const
>>> -{ /* NOT YET IMPLEMENTED */ }
>>> + int *Value, RegScavenger *RS) const
>>> +{
>>> + /* NOT YET IMPLEMENTED */
>>> + return 0;
>>> +}
>>>
>>> void PIC16RegisterInfo::emitPrologue(MachineFunction &MF) const
>>> { /* NOT YET IMPLEMENTED */ }
>>>
>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -48,8 +48,9 @@
>>> virtual BitVector getReservedRegs(const MachineFunction &MF) const;
>>> virtual bool hasFP(const MachineFunction &MF) const;
>>>
>>> - virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
>>> - int SPAdj, RegScavenger *RS=NULL) const;
>>> + virtual unsigned eliminateFrameIndex
>>> (MachineBasicBlock::iterator MI,
>>> + int SPAdj, int *Value =
>>> NULL,
>>> + RegScavenger *RS=NULL)
>>> const;
>>>
>>> void eliminateCallFramePseudoInstr(MachineFunction &MF,
>>> MachineBasicBlock &MBB,
>>>
>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -699,8 +699,10 @@
>>> MBB.erase(II);
>>> }
>>>
>>> -void PPCRegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger
>>> *RS) const {
>>> +unsigned
>>> +PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator
>>> II,
>>> + int SPAdj, int *Value,
>>> + RegScavenger *RS) const {
>>> assert(SPAdj == 0 && "Unexpected");
>>>
>>> // Get the instruction.
>>> @@ -739,14 +741,14 @@
>>> if (FPSI && FrameIndex == FPSI &&
>>> (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
>>> lowerDynamicAlloc(II, SPAdj, RS);
>>> - return;
>>> + return 0;
>>> }
>>>
>>> // Special case for pseudo-op SPILL_CR.
>>> if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
>>> if (OpC == PPC::SPILL_CR) {
>>> lowerCRSpilling(II, FrameIndex, SPAdj, RS);
>>> - return;
>>> + return 0;
>>> }
>>>
>>> // Replace the FrameIndex with base register with GPR1 (SP) or
>>> GPR31 (FP).
>>> @@ -788,7 +790,7 @@
>>> if (isIXAddr)
>>> Offset >>= 2; // The actual encoded value has the low two
>>> bits zero.
>>> MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
>>> - return;
>>> + return 0;
>>> }
>>>
>>> // The offset doesn't fit into a single register, scavenge one to
>>> build the
>>> @@ -828,6 +830,7 @@
>>> unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
>>> MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
>>> MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
>>> + return 0;
>>> }
>>>
>>> /// VRRegNo - Map from a numbered VR register to its enum value.
>>>
>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -66,8 +66,9 @@
>>> int SPAdj, RegScavenger *RS) const;
>>> void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned
>>> FrameIndex,
>>> int SPAdj, RegScavenger *RS) const;
>>> - void eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger *RS = NULL)
>>> const;
>>> + unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value = NULL,
>>> + RegScavenger *RS = NULL) const;
>>>
>>> /// determineFrameLayout - Determine the size of the frame and
>>> maximum call
>>> /// frame size.
>>>
>>> Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -76,8 +76,10 @@
>>> MBB.erase(I);
>>> }
>>>
>>> -void SparcRegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> - int SPAdj,
>>> RegScavenger *RS) const {
>>> +unsigned
>>> +SparcRegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value,
>>> + RegScavenger *RS) const {
>>> assert(SPAdj == 0 && "Unexpected");
>>>
>>> unsigned i = 0;
>>> @@ -113,6 +115,7 @@
>>> MI.getOperand(i).ChangeToRegister(SP::G1, false);
>>> MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
>>> }
>>> + return 0;
>>> }
>>>
>>> void SparcRegisterInfo::
>>>
>>> Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -43,8 +43,9 @@
>>> MachineBasicBlock &MBB,
>>> MachineBasicBlock::iterator I)
>>> const;
>>>
>>> - void eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger *RS = NULL)
>>> const;
>>> + unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value = NULL,
>>> + RegScavenger *RS = NULL) const;
>>>
>>> void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp Wed Oct
>>> 7 12:12:56 2009
>>> @@ -107,8 +107,10 @@
>>> return Offset;
>>> }
>>>
>>> -void SystemZRegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> - int SPAdj,
>>> RegScavenger *RS) const {
>>> +unsigned
>>> +SystemZRegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value,
>>> + RegScavenger *RS) const {
>>> assert(SPAdj == 0 && "Unxpected");
>>>
>>> unsigned i = 0;
>>> @@ -136,6 +138,7 @@
>>> MI.setDesc(TII.getMemoryInstr(MI.getOpcode(), Offset));
>>>
>>> MI.getOperand(i+1).ChangeToImmediate(Offset);
>>> + return 0;
>>> }
>>>
>>> void
>>>
>>> Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -55,8 +55,9 @@
>>> MachineBasicBlock &MBB,
>>> MachineBasicBlock::iterator I)
>>> const;
>>>
>>> - void eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger *RS = NULL)
>>> const;
>>> + unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value = NULL,
>>> + RegScavenger *RS = NULL) const;
>>>
>>>
>>> void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
>>>
>>> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -579,8 +579,10 @@
>>> MBB.erase(I);
>>> }
>>>
>>> -void X86RegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger
>>> *RS) const{
>>> +unsigned
>>> +X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator
>>> II,
>>> + int SPAdj, int *Value,
>>> + RegScavenger *RS) const{
>>> assert(SPAdj == 0 && "Unexpected");
>>>
>>> unsigned i = 0;
>>> @@ -617,6 +619,7 @@
>>> (uint64_t)MI.getOperand(i+3).getOffset();
>>> MI.getOperand(i+3).setOffset(Offset);
>>> }
>>> + return 0;
>>> }
>>>
>>> void
>>>
>>> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -139,8 +139,9 @@
>>> MachineBasicBlock &MBB,
>>> MachineBasicBlock::iterator MI)
>>> const;
>>>
>>> - void eliminateFrameIndex(MachineBasicBlock::iterator MI,
>>> - int SPAdj, RegScavenger *RS = NULL)
>>> const;
>>> + unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
>>> + int SPAdj, int *Value = NULL,
>>> + RegScavenger *RS = NULL) const;
>>>
>>> void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
>>> RegScavenger *RS = NULL)
>>> const;
>>>
>>> Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Wed Oct 7
>>> 12:12:56 2009
>>> @@ -171,8 +171,10 @@
>>> MBB.erase(I);
>>> }
>>>
>>> -void XCoreRegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> - int SPAdj,
>>> RegScavenger *RS) const {
>>> +unsigned
>>> +XCoreRegisterInfo::eliminateFrameIndex
>>> (MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value,
>>> + RegScavenger *RS) const {
>>> assert(SPAdj == 0 && "Unexpected");
>>> MachineInstr &MI = *II;
>>> DebugLoc dl = MI.getDebugLoc();
>>> @@ -311,6 +313,7 @@
>>> }
>>> // Erase old instruction.
>>> MBB.erase(II);
>>> + return 0;
>>> }
>>>
>>> void
>>>
>>> Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h?rev=83467&r1=83466&r2=83467&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h (original)
>>> +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h Wed Oct 7
>>> 12:12:56 2009
>>> @@ -57,8 +57,9 @@
>>> MachineBasicBlock &MBB,
>>> MachineBasicBlock::iterator I)
>>> const;
>>>
>>> - void eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> - int SPAdj, RegScavenger *RS = NULL)
>>> const;
>>> + unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
>>> + int SPAdj, int *Value = NULL,
>>> + RegScavenger *RS = NULL) const;
>>>
>>> void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
>>> RegScavenger *RS =
>>> NULL) const;
>>>
>>>
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