[llvm-commits] [llvm] r83215 - in /llvm/trunk: lib/CodeGen/PostRASchedulerList.cpp lib/Target/ARM/ARM.td lib/Target/ARM/ARMSubtarget.cpp test/CodeGen/ARM/2009-08-21-PostRAKill.ll test/CodeGen/ARM/2009-08-21-PostRAKill2.ll test/CodeGen/ARM/2009-08-21-PostRAKill3.ll test/CodeGen/ARM/2009-08-21-PostRAKill4.ll test/CodeGen/ARM/2009-09-01-PostRAProlog.ll test/CodeGen/X86/break-anti-dependencies.ll
David Goodwin
david_goodwin at apple.com
Thu Oct 1 14:46:35 PDT 2009
Author: david_goodwin
Date: Thu Oct 1 16:46:35 2009
New Revision: 83215
URL: http://llvm.org/viewvc/llvm-project?rev=83215&view=rev
Log:
Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
Added:
llvm/trunk/test/CodeGen/X86/break-anti-dependencies.ll
Modified:
llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll
Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=83215&r1=83214&r2=83215&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Thu Oct 1 16:46:35 2009
@@ -48,11 +48,17 @@
STATISTIC(NumNoops, "Number of noops inserted");
STATISTIC(NumStalls, "Number of pipeline stalls");
+// Post-RA scheduling is enabled with
+// TargetSubtarget.enablePostRAScheduler(). This flag can be used to
+// override the target.
+static cl::opt<bool>
+EnablePostRAScheduler("post-RA-scheduler",
+ cl::desc("Enable scheduling after register allocation"),
+ cl::init(false));
static cl::opt<bool>
EnableAntiDepBreaking("break-anti-dependencies",
cl::desc("Break post-RA scheduling anti-dependencies"),
cl::init(true), cl::Hidden);
-
static cl::opt<bool>
EnablePostRAHazardAvoidance("avoid-hazards",
cl::desc("Enable exact hazard avoidance"),
@@ -215,10 +221,16 @@
}
bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
- // Check that post-RA scheduling is enabled for this function
- const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
- if (!ST.enablePostRAScheduler())
- return true;
+ // Check for explicit enable/disable of post-ra scheduling.
+ if (EnablePostRAScheduler.getPosition() > 0) {
+ if (!EnablePostRAScheduler)
+ return true;
+ } else {
+ // Check that post-RA scheduling is enabled for this function
+ const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
+ if (!ST.enablePostRAScheduler())
+ return true;
+ }
DEBUG(errs() << "PostRAScheduler\n");
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=83215&r1=83214&r2=83215&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Thu Oct 1 16:46:35 2009
@@ -43,9 +43,6 @@
def FeatureNEONFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
"true",
"Use NEON for single-precision FP">;
-def FeaturePostRASched : SubtargetFeature<"postrasched", "PostRAScheduler",
- "true",
- "Use Post-Register-Allocation Scheduler">;
//===----------------------------------------------------------------------===//
// ARM Processors supported.
@@ -108,8 +105,7 @@
// V7 Processors.
def : Processor<"cortex-a8", CortexA8Itineraries,
- [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP,
- FeaturePostRASched]>;
+ [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP]>;
def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=83215&r1=83214&r2=83215&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Oct 1 16:46:35 2009
@@ -93,6 +93,11 @@
if (isTargetDarwin())
IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
+
+ // Set CPU specific features.
+ if (CPUString == "cortex-a8") {
+ PostRAScheduler = true;
+ }
}
/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
Modified: llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill.ll?rev=83215&r1=83214&r2=83215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill.ll Thu Oct 1 16:46:35 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+vfp2,+postrasched -mcpu=cortex-a8
+; RUN: llc < %s -march=arm -mattr=+vfp2 -post-RA-scheduler -mcpu=cortex-a8
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll?rev=83215&r1=83214&r2=83215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll Thu Oct 1 16:46:35 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll?rev=83215&r1=83214&r2=83215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll Thu Oct 1 16:46:35 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll?rev=83215&r1=83214&r2=83215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll Thu Oct 1 16:46:35 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll?rev=83215&r1=83214&r2=83215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll Thu Oct 1 16:46:35 2009
@@ -1,5 +1,5 @@
; XFAIL: *
-; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched | FileCheck %s
+; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler | FileCheck %s
; ModuleID = '<stdin>'
Added: llvm/trunk/test/CodeGen/X86/break-anti-dependencies.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/break-anti-dependencies.ll?rev=83215&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/break-anti-dependencies.ll (added)
+++ llvm/trunk/test/CodeGen/X86/break-anti-dependencies.ll Thu Oct 1 16:46:35 2009
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=false > %t
+; RUN: grep {%xmm0} %t | count 14
+; RUN: not grep {%xmm1} %t
+; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies > %t
+; RUN: grep {%xmm0} %t | count 7
+; RUN: grep {%xmm1} %t | count 7
+
+define void @goo(double* %r, double* %p, double* %q) nounwind {
+entry:
+ %0 = load double* %p, align 8
+ %1 = fadd double %0, 1.100000e+00
+ %2 = fmul double %1, 1.200000e+00
+ %3 = fadd double %2, 1.300000e+00
+ %4 = fmul double %3, 1.400000e+00
+ %5 = fadd double %4, 1.500000e+00
+ %6 = fptosi double %5 to i32
+ %7 = load double* %r, align 8
+ %8 = fadd double %7, 7.100000e+00
+ %9 = fmul double %8, 7.200000e+00
+ %10 = fadd double %9, 7.300000e+00
+ %11 = fmul double %10, 7.400000e+00
+ %12 = fadd double %11, 7.500000e+00
+ %13 = fptosi double %12 to i32
+ %14 = icmp slt i32 %6, %13
+ br i1 %14, label %bb, label %return
+
+bb:
+ store double 9.300000e+00, double* %q, align 8
+ ret void
+
+return:
+ ret void
+}
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