[llvm-commits] [llvm] r83197 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrNEON.td ARMInstrThumb.td ARMInstrThumb2.td ARMInstrVFP.td
Evan Cheng
evan.cheng at apple.com
Thu Oct 1 01:22:27 PDT 2009
Author: evancheng
Date: Thu Oct 1 03:22:27 2009
New Revision: 83197
URL: http://llvm.org/viewvc/llvm-project?rev=83197&view=rev
Log:
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
ld / st pairs, etc.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=83197&r1=83196&r2=83197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Oct 1 03:22:27 2009
@@ -628,7 +628,8 @@
// FIXME: remove when we have a way to marking a MI with these properties.
// FIXME: Should pc be an implicit operand like PICADD, etc?
-let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1 in
+let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
+ hasExtraDefRegAllocReq = 1 in
def LDM_RET : AXI4ld<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
LdStMulFrm, IIC_Br, "ldm${p}${addr:submode} $addr, $wb",
@@ -783,7 +784,7 @@
IIC_iLoadr, "ldr", "sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
-let mayLoad = 1 in {
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
// Load doubleword
def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoadr, "ldr", "d $dst1, $addr",
@@ -846,7 +847,7 @@
[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
// Store doubleword
-let mayStore = 1 in
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
StMiscFrm, IIC_iStorer,
"str", "d $src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
@@ -898,13 +899,13 @@
// Load / store multiple Instructions.
//
-let mayLoad = 1 in
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
def LDM : AXI4ld<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
LdStMulFrm, IIC_iLoadm, "ldm${p}${addr:submode} $addr, $wb",
[]>;
-let mayStore = 1 in
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
def STM : AXI4st<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
LdStMulFrm, IIC_iStorem, "stm${p}${addr:submode} $addr, $wb",
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=83197&r1=83196&r2=83197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Oct 1 03:22:27 2009
@@ -107,7 +107,7 @@
//===----------------------------------------------------------------------===//
/* TODO: Take advantage of vldm.
-let mayLoad = 1 in {
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
def VLDMD : NI<(outs),
(ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
IIC_fpLoadm,
@@ -176,7 +176,7 @@
def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
-let mayLoad = 1 in {
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
// VLD2 : Vector Load (multiple 2-element structures)
class VLD2D<string OpcodeStr>
@@ -245,7 +245,7 @@
def VLD4LNd8 : VLD4LND<"vld4.8">;
def VLD4LNd16 : VLD4LND<"vld4.16">;
def VLD4LNd32 : VLD4LND<"vld4.32">;
-}
+} // mayLoad = 1, hasExtraDefRegAllocReq = 1
// VST1 : Vector Store (multiple single elements)
class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
@@ -257,6 +257,7 @@
!strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "",
[(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
+let hasExtraSrcRegAllocReq = 1 in {
def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1>;
def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1>;
@@ -268,8 +269,9 @@
def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
+} // hasExtraSrcRegAllocReq
-let mayStore = 1 in {
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
// VST2 : Vector Store (multiple 2-element structures)
class VST2D<string OpcodeStr>
@@ -334,7 +336,7 @@
def VST4LNd8 : VST4LND<"vst4.8">;
def VST4LNd16 : VST4LND<"vst4.16">;
def VST4LNd32 : VST4LND<"vst4.32">;
-}
+} // mayStore = 1, hasExtraSrcRegAllocReq = 1
//===----------------------------------------------------------------------===//
@@ -2550,6 +2552,7 @@
(ins DPR:$tbl1, DPR:$src), IIC_VTB1,
"vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
+let hasExtraSrcRegAllocReq = 1 in {
def VTBL2
: N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
(ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
@@ -2568,6 +2571,7 @@
"vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
+} // hasExtraSrcRegAllocReq = 1
// VTBX : Vector Table Extension
def VTBX1
@@ -2576,6 +2580,7 @@
"vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
+let hasExtraSrcRegAllocReq = 1 in {
def VTBX2
: N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
(ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
@@ -2594,6 +2599,7 @@
"vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
+} // hasExtraSrcRegAllocReq = 1
//===----------------------------------------------------------------------===//
// NEON instructions for single-precision FP math
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=83197&r1=83196&r2=83197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Oct 1 03:22:27 2009
@@ -181,7 +181,8 @@
}
// FIXME: remove when we have a way to marking a MI with these properties.
-let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1 in
+let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
+ hasExtraDefRegAllocReq = 1 in
def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
"pop${p} $wb", []>;
@@ -348,23 +349,23 @@
//
// These requires base address to be written back or one of the loaded regs.
-let mayLoad = 1 in
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
def tLDM : T1I<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
IIC_iLoadm,
"ldm${addr:submode}${p} $addr, $wb", []>;
-let mayStore = 1 in
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
def tSTM : T1I<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
IIC_iStorem,
"stm${addr:submode}${p} $addr, $wb", []>;
-let mayLoad = 1, Uses = [SP], Defs = [SP] in
+let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
"pop${p} $wb", []>;
-let mayStore = 1, Uses = [SP], Defs = [SP] in
+let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
"push${p} $wb", []>;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=83197&r1=83196&r2=83197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Oct 1 03:22:27 2009
@@ -461,7 +461,7 @@
defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
-let mayLoad = 1 in {
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
// Load doubleword
def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2),
(ins t2addrmode_imm8s4:$addr),
@@ -576,7 +576,7 @@
defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
// Store doubleword
-let mayLoad = 1 in
+let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
def t2STRDi8 : T2Ii8s4<(outs),
(ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
IIC_iStorer, "strd", " $src1, $addr", []>;
@@ -631,12 +631,12 @@
// Load / store multiple Instructions.
//
-let mayLoad = 1 in
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
def t2LDM : T2XI<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide} $addr, $wb", []>;
-let mayStore = 1 in
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
def t2STM : T2XI<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
IIC_iStorem, "stm${addr:submode}${p}${addr:wide} $addr, $wb", []>;
@@ -1072,7 +1072,8 @@
// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
// operand list.
// FIXME: Should pc be an implicit operand like PICADD, etc?
-let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1 in
+let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
+ hasExtraDefRegAllocReq = 1 in
def t2LDM_RET : T2XI<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
IIC_Br, "ldm${addr:submode}${p}${addr:wide} $addr, $wb",
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=83197&r1=83196&r2=83197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Thu Oct 1 03:22:27 2009
@@ -56,7 +56,7 @@
// Load / store multiple Instructions.
//
-let mayLoad = 1 in {
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
variable_ops), IIC_fpLoadm,
"fldm${addr:submode}d${p} ${addr:base}, $wb",
@@ -70,9 +70,9 @@
[]> {
let Inst{20} = 1;
}
-}
+} // mayLoad, hasExtraDefRegAllocReq
-let mayStore = 1 in {
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
variable_ops), IIC_fpStorem,
"fstm${addr:submode}d${p} ${addr:base}, $wb",
@@ -86,7 +86,7 @@
[]> {
let Inst{20} = 0;
}
-} // mayStore
+} // mayStore, hasExtraSrcRegAllocReq
// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
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