[llvm-commits] [llvm] r81878 - in /llvm/trunk: lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll

[Chris Lattner]

On Sep 15, 2009, at 10:53 AM, Sandeep Patel wrote:

> Author: sandeep
> Date: Tue Sep 15 12:53:11 2009
> New Revision: 81878
>
> URL: http://llvm.org/viewvc/llvm-project?rev=81878&view=rev
> Log:
> Fix superreg use in ARMAsmPrinter. Approved by Anton Korobeynikov.

Hi Sandeep,

Please make the test check for some expected output.  I will be  
hacking on the ARM asmprinter (to make it work like the new X86  
asmprinter) real-soon-now and don't want to regress anything.

-Chris

>
> Added:
>    llvm/trunk/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
> Modified:
>    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>
> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=81878&r1=81877&r2=81878&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Tue Sep  
> 15 12:53:11 2009
> @@ -318,8 +318,8 @@
>           << '}';
>       } else if (Modifier && strcmp(Modifier, "lane") == 0) {
>         unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
> -        unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ?  
> 0 : 1,
> -                                                 &ARM::DPRRegClass);
> +        unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ?  
> 2 : 1,
> +                                                  
> &ARM::DPR_VFP2RegClass);
>         O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
>       } else {
>         O << getRegisterName(Reg);
>
> Added: llvm/trunk/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll?rev=81878&view=auto
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll Tue  
> Sep 15 12:53:11 2009
> @@ -0,0 +1,41 @@
> +; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a9
> +
> +define arm_aapcs_vfpcc <4 x float> @foo(i8* nocapture %pBuffer, i32  
> %numItems) nounwind {
> +  %1 = ptrtoint i8* %pBuffer to i32
> +
> +  %lsr.iv2641 = inttoptr i32 %1 to float*
> +  %tmp29 = add i32 %1, 4
> +  %tmp2930 = inttoptr i32 %tmp29 to float*
> +  %tmp31 = add i32 %1, 8
> +  %tmp3132 = inttoptr i32 %tmp31 to float*
> +  %tmp33 = add i32 %1, 12
> +  %tmp3334 = inttoptr i32 %tmp33 to float*
> +  %tmp35 = add i32 %1, 16
> +  %tmp3536 = inttoptr i32 %tmp35 to float*
> +  %tmp37 = add i32 %1, 20
> +  %tmp3738 = inttoptr i32 %tmp37 to float*
> +  %tmp39 = add i32 %1, 24
> +  %tmp3940 = inttoptr i32 %tmp39 to float*
> +  %2 = load float* %lsr.iv2641, align 4
> +  %3 = load float* %tmp2930, align 4
> +  %4 = load float* %tmp3132, align 4
> +  %5 = load float* %tmp3334, align 4
> +  %6 = load float* %tmp3536, align 4
> +  %7 = load float* %tmp3738, align 4
> +  %8 = load float* %tmp3940, align 4
> +  %9 = insertelement <4 x float> undef, float %6, i32 0
> +  %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32>  
> zeroinitializer
> +  %11 = insertelement <4 x float> %10, float %7, i32 1
> +  %12 = insertelement <4 x float> %11, float %8, i32 2
> +  %13 = insertelement <4 x float> undef, float %2, i32 0
> +  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32>  
> zeroinitializer
> +  %15 = insertelement <4 x float> %14, float %3, i32 1
> +  %16 = insertelement <4 x float> %15, float %4, i32 2
> +  %17 = insertelement <4 x float> %16, float %5, i32 3
> +  %18 = fsub <4 x float> zeroinitializer, %12
> +  %19 = shufflevector <4 x float> %18, <4 x float> undef, <4 x i32>  
> zeroinitializer
> +  %20 = shufflevector <4 x float> %17, <4 x float> undef, <2 x i32>  
> <i32 0, i32 1>
> +  %21 = shufflevector <2 x float> %20, <2 x float> undef, <4 x i32>  
> <i32 1, i32 1, i32 1, i32 1>
> +
> +  ret <4 x float> %21
> +}
>
>
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