[llvm-commits] [llvm] r81657 - in /llvm/trunk: lib/Target/ARM/ARMRegisterInfo.td test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll

[Anton Korobeynikov]

Hello, Evan

> Could you explain why this is needed?
ARM 'high' D / Q registers don't have 32-bit subregs. Previously we
incorrectly claimed that all Q / D registers do have them. This
confuses the codegen while computing superregs - it was allowed to
have e.g. Q8 as a superreg of 32-bit subreg, which is definitely
incorrect.

We discussed the PR in question with Bob and decided that proper
solution will be to model subregs properly. All other solutions turned
out to be pretty fragile. The dummy subclass is needed since we want
to have same subreg indices for both QPR and QPR_VFP2 reglcass.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University