[llvm-commits] [llvm] r81658 - /llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td

[Anton Korobeynikov]

Author: asl
Date: Sat Sep 12 20:12:15 2009
New Revision: 81658

URL: http://llvm.org/viewvc/llvm-project?rev=81658&view=rev
Log:
Fix merge problem

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=81658&r1=81657&r2=81658&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Sat Sep 12 20:12:15 2009
@@ -347,13 +347,6 @@
   let SubRegClassList = [SPR, SPR, SPR, SPR, DPR_VFP2, DPR_VFP2];
 }
 
-// Subset of QPR that have 32-bit SPR subregs.
-def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
-                             128,
-                             [Q0,  Q1,  Q2,  Q3,  Q4,  Q5,  Q6,  Q7]> {
-  let SubRegClassList = [SPR, SPR, SPR, SPR, DPR, DPR];
-}
-
 // Condition code registers.
 def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;