[llvm-commits] [llvm] r81560 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp

[Jim Grosbach]

Author: grosbach
Date: Fri Sep 11 15:13:17 2009
New Revision: 81560

URL: http://llvm.org/viewvc/llvm-project?rev=81560&view=rev
Log:
Revert array initialization regclass change so that the initialization stays static, not runtime.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=81560&r1=81559&r2=81560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Fri Sep 11 15:13:17 2009
@@ -164,46 +164,42 @@
 const TargetRegisterClass* const *
 ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
   static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
-    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
-    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
-    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
-
-    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
-    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
-    ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+
+    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
     0
   };
 
   static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
-    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
-    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::tGPRRegisterClass,
-    ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,
-
-    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
-    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
-    ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
+    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
+
+    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
     0
   };
 
   static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
-    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
-    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
-    ARM::GPRRegisterClass, ARM::GPRRegisterClass,
-
-    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
-    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
-    ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+    &ARM::GPRRegClass, &ARM::GPRRegClass,
+
+    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
     0
   };
 
   static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
-    ARM::GPRRegisterClass,  ARM::tGPRRegisterClass, ARM::tGPRRegisterClass,
-    ARM::tGPRRegisterClass, ARM::tGPRRegisterClass, ARM::GPRRegisterClass,
-    ARM::GPRRegisterClass,  ARM::GPRRegisterClass,
-
-    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
-    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
-    ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
+    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
+    &ARM::GPRRegClass,  &ARM::GPRRegClass,
+
+    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
     0
   };