[llvm-commits] [llvm] r81556 - in /llvm/trunk/lib/Target/ARM: ARMBaseRegisterInfo.cpp ARMLoadStoreOptimizer.cpp

[Jim Grosbach]

On Sep 11, 2009, at 1:01 PM, Chris Lattner wrote:

>
> On Sep 11, 2009, at 12:49 PM, Jim Grosbach wrote:
>
>> Author: grosbach
>> Date: Fri Sep 11 14:49:06 2009
>> New Revision: 81556
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=81556&view=rev
>> Log:
>> Update register class references to use the global constant  
>> ARM::*RegisterClass names.
>
> Why do you want to do this?  This will change the array from being  
> static to being runtime initialized.
>

Consistency of usage. There was a mixture of which form was used, and  
using the global constant is more readable. For the array  
initialization, however, that's a good reason to do otherwise. I'll  
revert that part.

> -Chris
>
>>
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
>>   llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=81556&r1=81555&r2=81556&view=diff
>>
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Fri Sep 11  
>> 14:49:06 2009
>> @@ -164,42 +164,46 @@
>> const TargetRegisterClass* const *
>> ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction  
>> *MF) const {
>>  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
>> -    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
>> -    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
>> -    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
>> -
>> -    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,  
>> &ARM::DPRRegClass,
>> -    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,  
>> &ARM::DPRRegClass,
>> +    ARM::GPRRegisterClass, ARM::GPRRegisterClass,  
>> ARM::GPRRegisterClass,
>> +    ARM::GPRRegisterClass, ARM::GPRRegisterClass,  
>> ARM::GPRRegisterClass,
>> +    ARM::GPRRegisterClass, ARM::GPRRegisterClass,  
>> ARM::GPRRegisterClass,
>> +
>> +    ARM::DPRRegisterClass, ARM::DPRRegisterClass,  
>> ARM::DPRRegisterClass,
>> +    ARM::DPRRegisterClass, ARM::DPRRegisterClass,  
>> ARM::DPRRegisterClass,
>> +    ARM::DPRRegisterClass, ARM::DPRRegisterClass,
>>    0
>>  };
>>
>>  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses 
>> [] = {
>> -    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
>> -    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
>> -    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
>> -
>> -    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,  
>> &ARM::DPRRegClass,
>> -    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,  
>> &ARM::DPRRegClass,
>> +    ARM::GPRRegisterClass, ARM::GPRRegisterClass,  
>> ARM::GPRRegisterClass,
>> +    ARM::GPRRegisterClass, ARM::GPRRegisterClass,  
>> ARM::tGPRRegisterClass,
>> +     
>> ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,
>> +
>> +    ARM::DPRRegisterClass, ARM::DPRRegisterClass,  
>> ARM::DPRRegisterClass,
>> +    ARM::DPRRegisterClass, ARM::DPRRegisterClass,  
>> ARM::DPRRegisterClass,
>> +    ARM::DPRRegisterClass, ARM::DPRRegisterClass,
>>    0
>>  };
>>
>>  static const TargetRegisterClass * const  
>> DarwinCalleeSavedRegClasses[] = {
>> -    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
>> -    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
>> -    &ARM::GPRRegClass, &ARM::GPRRegClass,
>> -
>> -    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,  
>> &ARM::DPRRegClass,
>> -    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,  
>> &ARM::DPRRegClass,
>> +    ARM::GPRRegisterClass, ARM::GPRRegisterClass,  
>> ARM::GPRRegisterClass,
>> +    ARM::GPRRegisterClass, ARM::GPRRegisterClass,  
>> ARM::GPRRegisterClass,
>> +    ARM::GPRRegisterClass, ARM::GPRRegisterClass,
>> +
>> +    ARM::DPRRegisterClass, ARM::DPRRegisterClass,  
>> ARM::DPRRegisterClass,
>> +    ARM::DPRRegisterClass, ARM::DPRRegisterClass,  
>> ARM::DPRRegisterClass,
>> +    ARM::DPRRegisterClass, ARM::DPRRegisterClass,
>>    0
>>  };
>>
>>  static const TargetRegisterClass * const  
>> DarwinThumbCalleeSavedRegClasses[] ={
>> -    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
>> -    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
>> -    &ARM::GPRRegClass,  &ARM::GPRRegClass,
>> -
>> -    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,  
>> &ARM::DPRRegClass,
>> -    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,  
>> &ARM::DPRRegClass,
>> +    ARM::GPRRegisterClass,  ARM::tGPRRegisterClass,  
>> ARM::tGPRRegisterClass,
>> +    ARM::tGPRRegisterClass, ARM::tGPRRegisterClass,  
>> ARM::GPRRegisterClass,
>> +    ARM::GPRRegisterClass,  ARM::GPRRegisterClass,
>> +
>> +    ARM::DPRRegisterClass, ARM::DPRRegisterClass,  
>> ARM::DPRRegisterClass,
>> +    ARM::DPRRegisterClass, ARM::DPRRegisterClass,  
>> ARM::DPRRegisterClass,
>> +    ARM::DPRRegisterClass, ARM::DPRRegisterClass,
>>    0
>>  };
>>
>> @@ -245,7 +249,7 @@
>>
>> const TargetRegisterClass *
>> ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
>> -  return &ARM::GPRRegClass;
>> +  return ARM::GPRRegisterClass;
>> }
>>
>> /// getAllocationOrder - Returns the register allocation order for  
>> a specified
>> @@ -536,7 +540,7 @@
>>      }
>>    }
>>
>> -    if (CSRegClasses[i] == &ARM::GPRRegClass) {
>> +    if (CSRegClasses[i] == ARM::GPRRegisterClass) {
>>      if (Spilled) {
>>        NumGPRSpills++;
>>
>> @@ -680,7 +684,7 @@
>>          }
>>        } else {
>>          // Reserve a slot closest to SP or frame pointer.
>> -          const TargetRegisterClass *RC = &ARM::GPRRegClass;
>> +          const TargetRegisterClass *RC = ARM::GPRRegisterClass;
>>          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC- 
>> >getSize(),
>>                                                           RC- 
>> >getAlignment()));
>>        }
>> @@ -1068,10 +1072,10 @@
>>  // If the offset we have is too large to fit into the instruction,  
>> we need
>>  // to form it with a series of ADDri's.  Do this by taking 8-bit  
>> chunks
>>  // out of 'Offset'.
>> -  unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass,  
>> AFI);
>> +  unsigned ScratchReg = findScratchRegister(RS,  
>> ARM::GPRRegisterClass, AFI);
>>  if (ScratchReg == 0)
>>    // No register is "free". Scavenge a register.
>> -    ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
>> +    ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II,  
>> SPAdj);
>>  int PIdx = MI.findFirstPredOperandIdx();
>>  ARMCC::CondCodes Pred = (PIdx == -1)
>>    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=81556&r1=81555&r2=81556&view=diff
>>
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Fri Sep 11  
>> 14:49:06 2009
>> @@ -942,7 +942,7 @@
>>        // First advance to the instruction just before the start of  
>> the chain.
>>        AdvanceRS(MBB, MemOps);
>>        // Find a scratch register.
>> -        unsigned Scratch = RS->FindUnusedReg(&ARM::GPRRegClass);
>> +        unsigned Scratch = RS->FindUnusedReg(ARM::GPRRegisterClass);
>>        // Process the load / store instructions.
>>        RS->forward(prior(MBBI));
>>
>>
>>
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>