[llvm-commits] [llvm] r81496 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll

[Evan Cheng]

Author: evancheng
Date: Thu Sep 10 20:01:31 2009
New Revision: 81496

URL: http://llvm.org/viewvc/llvm-project?rev=81496&view=rev
Log:
Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=81496&r1=81495&r2=81496&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Sep 10 20:01:31 2009
@@ -2206,6 +2206,7 @@
       unsigned MinAlign = I->second.second;
       if (Align < MinAlign)
         return NULL;
+      bool NarrowToMOV32rm = false;
       if (Size) {
         unsigned RCSize =  MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
         if (Size < RCSize) {
@@ -2216,7 +2217,10 @@
           // If this is a 64-bit load, but the spill slot is 32, then we can do
           // a 32-bit load which is implicitly zero-extended. This likely is due
           // to liveintervalanalysis remat'ing a load from stack slot.
+          if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
+            return NULL;
           Opcode = X86::MOV32rm;
+          NarrowToMOV32rm = true;
         }
       }
 
@@ -2224,6 +2228,18 @@
         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
       else
         NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
+
+      if (NarrowToMOV32rm) {
+        // If this is the special case where we use a MOV32rm to load a 32-bit
+        // value and zero-extend the top bits. Change the destination register
+        // to a 32-bit one.
+        unsigned DstReg = NewMI->getOperand(0).getReg();
+        if (TargetRegisterInfo::isPhysicalRegister(DstReg))
+          NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
+                                                   4/*x86_subreg_32bit*/));
+        else
+          NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
+      }
       return NewMI;
     }
   }

Modified: llvm/trunk/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll?rev=81496&r1=81495&r2=81496&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll Thu Sep 10 20:01:31 2009
@@ -13,7 +13,7 @@
 entry:
 ; CHECK: _t:
 ; CHECK: movl 16(%rbp),
-; CHECK: movl 16(%rbp),
+; CHECK: movl 16(%rbp), %edx
   %0 = zext i32 %argumentsLength to i64           ; <i64> [#uses=1]
   %1 = zext i32 %clientPort to i64                ; <i64> [#uses=1]
   %2 = inttoptr i64 %1 to %struct.ComplexType*    ; <%struct.ComplexType*> [#uses=1]