[llvm-commits] [llvm] r81171 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-fneg.ll

[Bob Wilson]

Dan,

This is causing pr4927.  I'm going to revert it for now.

On Sep 7, 2009, at 4:47 PM, Dan Gohman wrote:

> Author: djg
> Date: Mon Sep  7 18:47:14 2009
> New Revision: 81171
>
> URL: http://llvm.org/viewvc/llvm-project?rev=81171&view=rev
> Log:
> Fix a thinko: When lowering fneg with xor, bitcast the operands
> from floating-point to integer first, and bitcast the result
> back to floating-point. Previously, this test was passing by
> falling back to SelectionDAG lowering. The resulting code isn't
> as nice, but it's correct and CodeGen now stays on the fast path.
>
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>    llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=81171&r1=81170&r2=81171&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Sep  7  
> 18:47:14 2009
> @@ -615,12 +615,25 @@
>   unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
>   if (OpReg == 0) return false;
>
> -  // Twiddle the sign bit with xor.
> +  // Bitcast the value to integer, twiddle the sign bit with xor,
> +  // and then bitcast it back to floating-point.
>   EVT VT = TLI.getValueType(I->getType());
>   if (VT.getSizeInBits() > 64) return false;
> -  unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISD::XOR,  
> OpReg,
> -                                    UINT64_C(1) << (VT.getSizeInBits 
> ()-1),
> -                                    VT.getSimpleVT());
> +  EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
> +
> +  unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
> +                               ISD::BIT_CONVERT, OpReg);
> +  if (IntReg == 0)
> +    return false;
> +
> +  unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(),  
> ISD::XOR, IntReg,
> +                                       UINT64_C(1) <<  
> (VT.getSizeInBits()-1),
> +                                       IntVT.getSimpleVT());
> +  if (IntResultReg == 0)
> +    return false;
> +
> +  unsigned ResultReg = FastEmit_r(IntVT.getSimpleVT(),  
> VT.getSimpleVT(),
> +                                  ISD::BIT_CONVERT, IntResultReg);
>   if (ResultReg == 0)
>     return false;
>
>
> Modified: llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll?rev=81171&r1=81170&r2=81171&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll Mon Sep  7  
> 18:47:14 2009
> @@ -1,14 +1,14 @@
> -; RUN: llvm-as < %s | llc -fast-isel -march=x86-64 | FileCheck %s
> +; RUN: llvm-as < %s | llc -fast-isel -fast-isel-abort -march=x86-64  
> | FileCheck %s
>
> ; CHECK: doo:
> -; CHECK: xorpd
> +; CHECK: xor
> define double @doo(double %x) nounwind {
>   %y = fsub double -0.0, %x
>   ret double %y
> }
>
> ; CHECK: foo:
> -; CHECK: xorps
> +; CHECK: xor
> define float @foo(float %x) nounwind {
>   %y = fsub float -0.0, %x
>   ret float %y
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits