[llvm-commits] [llvm] r80245 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMInstrNEON.td

[Evan Cheng]

On Aug 27, 2009, at 7:38 AM, Anton Korobeynikov <asl at math.spbu.ru>  
wrote:

> Author: asl
> Date: Thu Aug 27 09:38:44 2009
> New Revision: 80245
>
> URL: http://llvm.org/viewvc/llvm-project?rev=80245&view=rev
> Log:
> Transform float scalar_to_vector into subreg accesses.
> No idea whether this is profitable or not.
>

It's the right thing to do. If it somehow hurts performance, please  
file a bug and assign it to me.

Evan

> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=80245&r1=80244&r2=80245&view=diff
>
> === 
> === 
> === 
> =====================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 27  
> 09:38:44 2009
> @@ -78,7 +78,7 @@
>     setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(),  
> Custom);
>   setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
>   setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
> -  setOperationAction(ISD::SCALAR_TO_VECTOR, VT.getSimpleVT(),  
> Expand);
> +  setOperationAction(ISD::SCALAR_TO_VECTOR, VT.getSimpleVT(),  
> Custom);
>   setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
>   setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(),  
> Expand);
>   if (VT.isInteger()) {
> @@ -2706,6 +2706,12 @@
> }
>
> static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
> +  EVT VT = Op.getValueType();
> +  EVT EltVT = VT.getVectorElementType();
> +
> +  if (EltVT.isInteger())
> +    return SDValue();
> +
>   return Op;
> }
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=80245&r1=80244&r2=80245&view=diff
>
> === 
> === 
> === 
> =====================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Aug 27 09:38:44 2009
> @@ -1726,6 +1726,13 @@
> def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
>           (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm: 
> $src3))>;
>
> +def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
> +          (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src,  
> arm_ssubreg_0)>;
> +def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
> +          (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src,  
> arm_dsubreg_0)>;
> +def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
> +          (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src,  
> arm_ssubreg_0)>;
> +
> //   VDUP     : Vector Duplicate (from ARM core register to all  
> elements)
>
> class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize,  
> ValueType Ty>
>
>
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