[llvm-commits] [llvm] r80244 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Misha Brukman]

Author: brukman
Date: Thu Aug 27 09:14:21 2009
New Revision: 80244

URL: http://llvm.org/viewvc/llvm-project?rev=80244&view=rev
Log:
STRD and LDRD require ARMv5TE, not just ARMv5T.
See http://llvm.org/PR4687 for more info and links.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=80244&r1=80243&r2=80244&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Aug 27 09:14:21 2009
@@ -767,7 +767,7 @@
 // Load doubleword
 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
                  IIC_iLoadr, "ldr", "d $dst1, $addr",
-                 []>, Requires<[IsARM, HasV5T]>;
+                 []>, Requires<[IsARM, HasV5TE]>;
 
 // Indexed loads
 def LDR_PRE  : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
@@ -829,7 +829,7 @@
 let mayStore = 1 in
 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
                StMiscFrm, IIC_iStorer,
-               "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>;
+               "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
 
 // Indexed stores
 def STR_PRE  : AI2stwpr<(outs GPR:$base_wb),