[llvm-commits] [llvm] r79377 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h X86InstrFormats.td X86InstrSSE.td

[Chris Lattner]

On Aug 19, 2009, at 12:43 AM, Eric Christopher wrote:

>>
>> Did you try writing the pattern as (set XMM0, (...))?
>>
>> Fixed registers work for other instructions, for example, we have:
>>
>> let Defs = [ECX, EFLAGS] in {
>> multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
>>   def rr : SS42AI<0x63, MRMSrcReg, (outs),
>>               (ins VR128:$src1, VR128:$src2, i8imm:$src3),
>>               "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
>>               [(set ECX,
>>                  (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
>>                (implicit EFLAGS)]>,
>>               OpSize;
>>
>> which produces a fixed result in ECX, doesn't the same work for XMM0?
>
> Nope, it can be any of a number of different register types and  
> there is no register class for just XMM0. i.e. it comes out as  
> MVT::Other.  We could define a custom register class for it as about  
> the only other way.

Hi Eric,

I still don't understand what the problem is here.  Is the problem  
you're solving a type inference issue?  If so, you can fix it by doing  
something like:


(set (v4i32 XMM0), ...)

or better yet:

(set XMM0, (v4i32 ... ))

Is this the problem, or is there something else going on?  We'd prefer  
to have as little custom c++ matching code as possible for obvious  
reasons :)

-Chris