[llvm-commits] [llvm] r79625 - in /llvm/trunk/lib/Target/ARM: ARMISelDAGToDAG.cpp ARMISelLowering.cpp ARMISelLowering.h ARMInstrNEON.td
Anton Korobeynikov
asl at math.spbu.ru
Fri Aug 21 05:41:42 PDT 2009
Author: asl
Date: Fri Aug 21 07:41:42 2009
New Revision: 79625
URL: http://llvm.org/viewvc/llvm-project?rev=79625&view=rev
Log:
Fix some typos and use type-based isel for VZIP/VUZP/VTRN
Modified:
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=79625&r1=79624&r2=79625&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Aug 21 07:41:42 2009
@@ -1415,34 +1415,55 @@
N->getOperand(4), N->getOperand(5), Chain };
return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
}
- case ARMISD::VZIP16: {
+ case ARMISD::VZIP: {
+ unsigned Opc = 0;
EVT VT = N->getValueType(0);
- return CurDAG->getTargetNode(ARM::VZIPd16, dl, VT, VT,
- N->getOperand(0), N->getOperand(1));
- }
- case ARMISD::VZIP32: {
- EVT VT = N->getValueType(0);
- return CurDAG->getTargetNode(ARM::VZIPq32, dl, VT, VT,
- N->getOperand(0), N->getOperand(1));
- }
- case ARMISD::VUZP16: {
- EVT VT = N->getValueType(0);
- return CurDAG->getTargetNode(ARM::VUZPd16, dl, VT, VT,
- N->getOperand(0), N->getOperand(1));
- }
- case ARMISD::VUZP32: {
- EVT VT = N->getValueType(0);
- return CurDAG->getTargetNode(ARM::VUZPq32, dl, VT, VT,
- N->getOperand(0), N->getOperand(1));
- }
- case ARMISD::VTRN16: {
- EVT VT = N->getValueType(0);
- return CurDAG->getTargetNode(ARM::VTRNd16, dl, VT, VT,
- N->getOperand(0), N->getOperand(1));
- }
- case ARMISD::VTRN32: {
- EVT VT = N->getValueType(0);
- return CurDAG->getTargetNode(ARM::VTRNq32, dl, VT, VT,
+ switch (VT.getSimpleVT().SimpleTy) {
+ default: return NULL;
+ case MVT::v8i8: Opc = ARM::VZIPd8; break;
+ case MVT::v4i16: Opc = ARM::VZIPd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VZIPd32; break;
+ case MVT::v16i8: Opc = ARM::VZIPq8; break;
+ case MVT::v8i16: Opc = ARM::VZIPq16; break;
+ case MVT::v4f32:
+ case MVT::v4i32: Opc = ARM::VZIPq32; break;
+ }
+ return CurDAG->getTargetNode(Opc, dl, VT, VT,
+ N->getOperand(0), N->getOperand(1));
+ }
+ case ARMISD::VUZP: {
+ unsigned Opc = 0;
+ EVT VT = N->getValueType(0);
+ switch (VT.getSimpleVT().SimpleTy) {
+ default: return NULL;
+ case MVT::v8i8: Opc = ARM::VUZPd8; break;
+ case MVT::v4i16: Opc = ARM::VUZPd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VUZPd32; break;
+ case MVT::v16i8: Opc = ARM::VUZPq8; break;
+ case MVT::v8i16: Opc = ARM::VUZPq16; break;
+ case MVT::v4f32:
+ case MVT::v4i32: Opc = ARM::VUZPq32; break;
+ }
+ return CurDAG->getTargetNode(Opc, dl, VT, VT,
+ N->getOperand(0), N->getOperand(1));
+ }
+ case ARMISD::VTRN: {
+ unsigned Opc = 0;
+ EVT VT = N->getValueType(0);
+ switch (VT.getSimpleVT().SimpleTy) {
+ default: return NULL;
+ case MVT::v8i8: Opc = ARM::VTRNd8; break;
+ case MVT::v4i16: Opc = ARM::VTRNd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VTRNd32; break;
+ case MVT::v16i8: Opc = ARM::VTRNq8; break;
+ case MVT::v8i16: Opc = ARM::VTRNq16; break;
+ case MVT::v4f32:
+ case MVT::v4i32: Opc = ARM::VTRNq32; break;
+ }
+ return CurDAG->getTargetNode(Opc, dl, VT, VT,
N->getOperand(0), N->getOperand(1));
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=79625&r1=79624&r2=79625&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Aug 21 07:41:42 2009
@@ -493,15 +493,9 @@
case ARMISD::VREV64: return "ARMISD::VREV64";
case ARMISD::VREV32: return "ARMISD::VREV32";
case ARMISD::VREV16: return "ARMISD::VREV16";
- case ARMISD::VZIP32: return "ARMISD::VZIP32";
- case ARMISD::VZIP16: return "ARMISD::VZIP16";
- case ARMISD::VZIP8: return "ARMISD::VZIP8";
- case ARMISD::VUZP32: return "ARMISD::VUZP32";
- case ARMISD::VUZP16: return "ARMISD::VUZP16";
- case ARMISD::VUZP8: return "ARMISD::VUZP8";
- case ARMISD::VTRN32: return "ARMISD::VTRN32";
- case ARMISD::VTRN16: return "ARMISD::VTRN16";
- case ARMISD::VTRN8: return "ARMISD::VTRN8";
+ case ARMISD::VZIP: return "ARMISD::VZIP";
+ case ARMISD::VUZP: return "ARMISD::VUZP";
+ case ARMISD::VTRN: return "ARMISD::VTRN";
}
}
@@ -2566,7 +2560,7 @@
case OP_VDUP2:
case OP_VDUP3:
return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
- OpLHS, DAG.getConstant(OpNum-OP_VDUP0+1, MVT::i32));
+ OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
case OP_VEXT1:
case OP_VEXT2:
case OP_VEXT3:
@@ -2575,19 +2569,16 @@
DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
case OP_VUZPL:
case OP_VUZPR:
- return DAG.getNode(VT.is64BitVector() ? ARMISD::VUZP16 : ARMISD::VUZP32,
- dl, DAG.getVTList(VT, VT),
+ return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
case OP_VZIPL:
case OP_VZIPR:
- return DAG.getNode(VT.is64BitVector() ? ARMISD::VZIP16 : ARMISD::VZIP32,
- dl, DAG.getVTList(VT, VT),
+ return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
case OP_VTRNL:
case OP_VTRNR:
- return DAG.getNode(VT.is64BitVector() ? ARMISD::VTRN16 : ARMISD::VTRN32,
- dl, DAG.getVTList(VT, VT),
- OpLHS, OpRHS).getValue(0);
+ return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
+ OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=79625&r1=79624&r2=79625&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Fri Aug 21 07:41:42 2009
@@ -133,15 +133,9 @@
VREV32, // reverse elements within 32-bit words
VREV16, // reverse elements within 16-bit halfwords
- VZIP32,
- VZIP16,
- VZIP8,
- VUZP32,
- VUZP16,
- VUZP8,
- VTRN32,
- VTRN16,
- VTRN8
+ VZIP, // zip
+ VUZP, // unzip
+ VTRN // transpose
};
}
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=79625&r1=79624&r2=79625&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Aug 21 07:41:42 2009
@@ -111,15 +111,9 @@
def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
-def NEONzip32 : SDNode<"ARMISD::VZIP32", SDTARMVSHUF2>;
-def NEONzip16 : SDNode<"ARMISD::VZIP16", SDTARMVSHUF2>;
-def NEONzip8 : SDNode<"ARMISD::VZIP8", SDTARMVSHUF2>;
-def NEONuzp32 : SDNode<"ARMISD::VUZP32", SDTARMVSHUF2>;
-def NEONuzp16 : SDNode<"ARMISD::VUZP16", SDTARMVSHUF2>;
-def NEONuzp8 : SDNode<"ARMISD::VUZP16", SDTARMVSHUF2>;
-def NEONtrn32 : SDNode<"ARMISD::VTRN32", SDTARMVSHUF2>;
-def NEONtrn16 : SDNode<"ARMISD::VTRN16", SDTARMVSHUF2>;
-def NEONtrn8 : SDNode<"ARMISD::VTRN8", SDTARMVSHUF2>;
+def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
+def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
+def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
//===----------------------------------------------------------------------===//
// NEON operand definitions
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