[llvm-commits] [llvm] r79415 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll

[Eli Friedman]

Author: efriedma
Date: Wed Aug 19 03:46:10 2009
New Revision: 79415

URL: http://llvm.org/viewvc/llvm-project?rev=79415&view=rev
Log:
PR4737: Fix a nasty bug in load narrowing with non-power-of-two types.


Added:
    llvm/trunk/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=79415&r1=79414&r2=79415&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Aug 19 03:46:10 2009
@@ -3466,7 +3466,8 @@
       // Is the shift amount a multiple of size of VT?
       if ((ShAmt & (EVTBits-1)) == 0) {
         N0 = N0.getOperand(0);
-        if (N0.getValueType().getSizeInBits() <= EVTBits)
+        // Is the load width a multiple of size of VT?
+        if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
           return SDValue();
       }
     }

Added: llvm/trunk/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll?rev=79415&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll Wed Aug 19 03:46:10 2009
@@ -0,0 +1,15 @@
+; RUN: llvm-as < %s | llc -march=x86 | FileCheck %s
+
+ at a = external global i96, align 4
+ at b = external global i64, align 8
+
+define void @c() nounwind {
+; CHECK: movl a+8, %eax
+  %srcval1 = load i96* @a, align 4
+  %sroa.store.elt2 = lshr i96 %srcval1, 64
+  %tmp = trunc i96 %sroa.store.elt2 to i64
+; CHECK: movl %eax, b
+; CHECK: movl $0, b+4
+  store i64 %tmp, i64* @b, align 8
+  ret void
+}