[llvm-commits] [llvm] r79380 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/shift-parts.ll

[Bill Wendling]

On Aug 18, 2009, at 4:36 PM, Dan Gohman wrote:

> Author: djg
> Date: Tue Aug 18 18:36:17 2009
> New Revision: 79380
>
> URL: http://llvm.org/viewvc/llvm-project?rev=79380&view=rev
> Log:
> Legalize the shift amount operand of SRL_PARTS, SHL_PARTS, and
> SRA_PARTS, as is done for SRL, SHL, and SRA.
>
> Added:
>    llvm/trunk/test/CodeGen/X86/shift-parts.ll
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=79380&r1=79379&r2=79380&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Aug 18  
> 18:36:17 2009
> @@ -898,6 +898,13 @@
>       if (!Ops[1].getValueType().isVector())
>         Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
>       break;
> +    case ISD::SRL_PARTS:
> +    case ISD::SRA_PARTS:
> +    case ISD::SHL_PARTS:
> +      // Legalizing shifts/rotates requires adjusting the shift  
> amount
> +      // to the appropriate width.
> +      if (!Ops[2].getValueType().isVector())
> +        Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));

Should there be a "break;" statement here?

-bw

>     }
>
>     Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),
>
> Added: llvm/trunk/test/CodeGen/X86/shift-parts.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-parts.ll?rev=79380&view=auto
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/shift-parts.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/shift-parts.ll Tue Aug 18 18:36:17  
> 2009
> @@ -0,0 +1,22 @@
> +; RUN: llvm-as < %s | llc -march=x86-64 | grep shrdq
> +; PR4736
> +
> +%0 = type { i32, i8, [35 x i8] }
> +
> + at g_144 = external global %0, align 8              ; <%0*> [#uses=1]
> +
> +define i32 @int87(i32 %uint64p_8) nounwind {
> +entry:
> +  %srcval4 = load i320* bitcast (%0* @g_144 to i320*), align 8 ;  
> <i320> [#uses=1]
> +  br label %for.cond
> +
> +for.cond:                                         ; preds =  
> %for.cond, %entry
> +  %call3.in.in.in.v = select i1 undef, i320 192, i320 128 ; <i320>  
> [#uses=1]
> +  %call3.in.in.in = lshr i320 %srcval4, %call3.in.in.in.v ; <i320>  
> [#uses=1]
> +  %call3.in = trunc i320 %call3.in.in.in to i32   ; <i32> [#uses=1]
> +  %tobool = icmp eq i32 %call3.in, 0              ; <i1> [#uses=1]
> +  br i1 %tobool, label %for.cond, label %if.then
> +
> +if.then:                                          ; preds = %for.cond
> +  ret i32 1
> +}
>
>
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