[llvm-commits] [llvm] r79351 - in /llvm/trunk: lib/Target/XCore/XCoreTargetObjectFile.cpp test/CodeGen/XCore/globals.ll

[Richard Osborne]

Author: friedgold
Date: Tue Aug 18 12:58:17 2009
New Revision: 79351

URL: http://llvm.org/viewvc/llvm-project?rev=79351&view=rev
Log:
Put data with relocations in the same sections as data without relocations.

Modified:
    llvm/trunk/lib/Target/XCore/XCoreTargetObjectFile.cpp
    llvm/trunk/test/CodeGen/XCore/globals.ll

Modified: llvm/trunk/lib/Target/XCore/XCoreTargetObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetObjectFile.cpp?rev=79351&r1=79350&r2=79351&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetObjectFile.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetObjectFile.cpp Tue Aug 18 12:58:17 2009
@@ -51,5 +51,11 @@
       MCSectionXCore::Create(".cp.rodata", MCSectionELF::SHT_PROGBITS,
                              MCSectionELF::SHF_ALLOC |
                              MCSectionXCore::SHF_CP_SECTION,
-                             SectionKind::getReadOnly(), false, getContext());
+                             SectionKind::getReadOnlyWithRel(), false,
+                             getContext());
+
+  // Dynamic linking is not supported. Data with relocations is placed in the
+  // same section as data without relocations.
+  DataRelSection = DataRelLocalSection = DataSection;
+  DataRelROSection = DataRelROLocalSection = ReadOnlySection;
 }

Modified: llvm/trunk/test/CodeGen/XCore/globals.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/globals.ll?rev=79351&r1=79350&r2=79351&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/XCore/globals.ll (original)
+++ llvm/trunk/test/CodeGen/XCore/globals.ll Tue Aug 18 12:58:17 2009
@@ -22,6 +22,43 @@
 	ret i32* @G3
 }
 
+define i32 **@addr_G4() {
+entry:
+; CHECK: addr_G4:
+; CHECK: ldaw r0, dp[G4]
+	ret i32** @G4
+}
+
+define i32 **@addr_G5() {
+entry:
+; CHECK: addr_G5:
+; CHECK: ldaw r11, cp[G5]
+; CHECK: mov r0, r11
+	ret i32** @G5
+}
+
+define i32 **@addr_G6() {
+entry:
+; CHECK: addr_G6:
+; CHECK: ldaw r0, dp[G6]
+	ret i32** @G6
+}
+
+define i32 **@addr_G7() {
+entry:
+; CHECK: addr_G7:
+; CHECK: ldaw r11, cp[G7]
+; CHECK: mov r0, r11
+	ret i32** @G7
+}
+
+define i32 *@addr_G8() {
+entry:
+; CHECK: addr_G8:
+; CHECK: ldaw r0, dp[G8]
+	ret i32* @G8
+}
+
 @G1 = global i32 4712
 ; CHECK: .section .dp.data,"awd", at progbits
 ; CHECK: G1:
@@ -34,3 +71,22 @@
 ; CHECK: .section .cp.rodata,"ac", at progbits
 ; CHECK: G3:
 
+ at G4 = global i32* @G1
+; CHECK: .section .dp.data,"awd", at progbits
+; CHECK: G4:
+
+ at G5 = constant i32* @G1
+; CHECK: .section .cp.rodata,"ac", at progbits
+; CHECK: G5:
+
+ at G6 = global i32* @G8
+; CHECK: .section .dp.data,"awd", at progbits
+; CHECK: G6:
+
+ at G7 = constant i32* @G8
+; CHECK: .section .cp.rodata,"ac", at progbits
+; CHECK: G7:
+
+ at G8 = internal global i32 9312
+; CHECK: .section .dp.data,"awd", at progbits
+; CHECK: G8: